EP4CE6E22C8N Altera, EP4CE6E22C8N Datasheet - Page 181
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EP4CE6E22C8N
Manufacturer Part Number
EP4CE6E22C8N
Description
IC CYCLONE IV FPGA 6K 144EQFP
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE6E22C8N
Number Of Logic Elements/cells
6272
Number Of Labs/clbs
392
Total Ram Bits
270000
Number Of I /o
91
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-EQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
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Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
Figure 8–4. Multi-Device AS Configuration in Which Devices Receive the Same Data with Multiple .sof
Notes to
(1) Connect the pull-up resistors to the V
(2) Connect the pull-up resistor to the V
(3) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. You must set the master device in AS mode and the slave
(5) Connect the series resistor at the near end of the serial configuration device.
(6) Connect the repeater buffers between the master and slave devices for DATA[0] and DCLK. All I/O inputs must maintain a maximum AC voltage
(7) The 50- series resistors are optional if the 3.3-V configuration voltage standard is applied. For optimal signal integrity, connect these 50- series
(8) These pins are dual-purpose I/O pins. The nCSO pin functions as FLASH_nCE pin in AP mode. The ASDO pin functions as DATA[1] pin in AP
(9) Only Cyclone IV GX devices have an option to select CLKUSR (40 MHz maximum) as the external clock source for DCLK.
© December 2010 Altera Corporation
Serial Configuration
devices in PS mode. To connect the MSEL pins for the master device in AS mode and the slave devices in PS mode, refer to
Table 8–4 on page
of 4.1 V. The output resistance of the repeater buffers must fit the maximum overshoot equation outlined in
Requirements” on page
resistors if the 2.5- or 3.0-V configuration voltage standard is applied.
and FPP modes.
Device
Figure
DCLK
DATA
ASDI
nCS
8–4:
50 Ω
25 Ω
8–8, and
10 kΩ
(5),
V
(5)
(7)
8–5.
GND
CCIO
Table 8–5 on page
(1)
DATA[0]
nSTATUS
CONF_DONE
nCONFIG
nCE
DCLK
nCSO (8)
ASDO (8)
10 kΩ
Cyclone IV Master Device
CCIO
V
CCIO
CCIO
50 Ω
supply voltage of the I/O bank in which the nCE pin resides.
supply of the bank in which the pin resides.
Buffers (6)
(1)
(7)
8–9. Connect the MSEL pins directly to V
10 kΩ
V
CLKUSR
CCIO
MSEL[ ]
nCEO
(1)
10 kΩ
V
CCIO
(2)
(9)
(4)
CCA
or GND.
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA[0]
DCLK
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA[0]
DCLK
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA[0]
DCLK
Cyclone IV Slave Device
Cyclone IV Slave Device
Cyclone IV Slave Device
Cyclone IV Device Handbook, Volume 1
“Configuration and JTAG Pin I/O
MSEL[ ]
MSEL[ ]
MSEL[ ]
nCEO
nCEO
nCEO
Table 8–3 on page
N.C. (3)
(4)
N.C. (3)
(4)
N.C. (3)
(4)
8–15
8–8,
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