EP3C5E144I7N Altera, EP3C5E144I7N Datasheet - Page 101

• Manufacturer Part Number: EP3C5E144I7N
• Description: IC CYCLONE III FPGA 5K 144 EQFP
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C5E144I7N

• Number Of Logic Elements/cells: 5136
• Number Of Labs/clbs: 321
• Total Ram Bits: 423936
• Number Of I /o: 94
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 144-EQFP
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 5136
• # I/os (max): 94
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 5136
• Ram Bits: 423936
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: EQFP
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2557

Cyclone III Device Family I/O Elements
© December 2009
CIII51007-3.2
Altera Corporation
This chapter describes the I/O features offered in the Cyclone
(Cyclone III and Cyclone III LS devices).
The I/O capabilities of the Cyclone III device family are driven by the diversification
of I/O standards in many low-cost applications, and the significant increase in
required I/O performance. Altera’s objective is to create a device that accommodates
your key board design needs with ease and flexibility.
The I/O flexibility of the Cyclone III device family is increased from the previous
generation low-cost FPGAs by allowing all I/O standards to be selected on all I/O
banks. Improvements to on-chip termination (OCT) support and the addition of true
differential buffers have eliminated the need for external resistors in many
applications, such as display system interfaces. Altera’s Quartus
completes the solution with powerful pin planning features that allow you to plan
and optimize I/O system designs even before the design files are available.
This chapter contains the following sections:
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Cyclone III device family I/O elements (IOEs) contain a bidirectional I/O buffer and
five registers for registering input, output, output-enable signals, and complete
embedded bidirectional single-data rate transfer. I/O pins support various
single-ended and differential I/O standards.
The IOE contains one input register, two output registers, and two output-enable
(OE) registers. The two output registers and two OE registers are used for DDR
applications. You can use input registers for fast setup times and output registers for
fast clock-to-output times. Additionally, you can use OE registers for fast
clock-to-output enable timing. You can use IOEs for input, output, or bidirectional
data paths.
“Cyclone III Device Family I/O Elements” on page 6–1
“I/O Element Features” on page 6–2
“OCT Support” on page 6–7
“I/O Standards” on page 6–11
“Termination Scheme for I/O Standards” on page 6–13
“I/O Banks” on page 6–16
“Pad Placement and DC Guidelines” on page 6–21
6. I/O Features in the Cyclone III
Cyclone III Device Handbook, Volume 1
®
III device family
Device Family
®
II software