EP3C5E144I7N Altera, EP3C5E144I7N Datasheet - Page 143

• Manufacturer Part Number: EP3C5E144I7N
• Description: IC CYCLONE III FPGA 5K 144 EQFP
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C5E144I7N

• Number Of Logic Elements/cells: 5136
• Number Of Labs/clbs: 321
• Total Ram Bits: 423936
• Number Of I /o: 94
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 144-EQFP
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 5136
• # I/os (max): 94
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 5136
• Ram Bits: 423936
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: EQFP
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2557

Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
Chapter Revision History
Chapter Revision History
Table 7–6. Chapter Revision History (Part 1 of 2)
© December 2009
December 2009
July 2009
June 2009
October 2008
Date
Altera Corporation
Table 7–6
Version
3.2
3.1
3.0
1.3
lists the revision history for this chapter.
Minor changes to the text.
Made minor correction to the part number.
Updated to include Cyclone III LS information
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Updated chapter part number.
Updated “Introduction” on page 7–1, “High-Speed I/O Interface” on
page 7–1, “High-Speed I/O Standards Support” on page 7–7, “LVDS I/O
Standard Support in Cyclone III Family Devices” on page 7–7, “Designing
with LVDS” on page 7–8, “BLVDS I/O Standard Support in Cyclone III Family
Devices” on page 7–8, “RSDS, Mini-LVDS, and PPDS I/O Standard Support in
Cyclone III Family Devices” on page 7–10, “LVPECL I/O Support in Cyclone III
Family Devices” on page 7–12, “Differential SSTL I/O Standard Support in
Cyclone III Family Devices” on page 7–13, and “Differential HSTL I/O
Standard Support in Cyclone III Family Devices” on page 7–14.
Updated Figure 7–1 on page 7–2, Figure 7–4 on page 7–9, and Figure 7–5 on
page 7–10.
Updated Table 7–1 on page 7–3, Table 7–2 on page 7–4, Table 7–3 on
page 7–5, and Table 7–4 on page 7–7.
Updated Table 7–2.
Updated Table 7–1.
Updated “BLVDS I/O Standard Support in Cyclone III Devices”.
Updated “Software Overview”.
Removed registered trademark symbols for RSDS and PPDS.
Removed any mention of “RSDS and PPDS are registered trademarks of
National Semiconductor” in this chapter.
Updated chapter to new template.
Changes Made
Cyclone III Device Handbook, Volume 1
7–19