EP3C5E144I7N Altera, EP3C5E144I7N Datasheet - Page 102

• Manufacturer Part Number: EP3C5E144I7N
• Description: IC CYCLONE III FPGA 5K 144 EQFP
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C5E144I7N

• Number Of Logic Elements/cells: 5136
• Number Of Labs/clbs: 321
• Total Ram Bits: 423936
• Number Of I /o: 94
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 144-EQFP
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 5136
• # I/os (max): 94
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 5136
• Ram Bits: 423936
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: EQFP
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2557

6–2
Figure 6–1. Cyclone III Device Family IOE in a Bidirectional I/O Configuration
I/O Element Features
Programmable Current Strength
Cyclone III Device Handbook, Volume 1
Interconnect
Column
or Row
io_clk[5..0]
data_in1
data_in0
Figure 6–1
The Cyclone III device family IOE offers a range of programmable features for an I/O
pin. These features increase the flexibility of I/O utilization and provide an
alternative to reduce the usage of external discrete components to on-chip, such as a
pull-up resistor and a diode.
The output buffer for each Cyclone III device family I/O pin has a programmable
current strength control for certain I/O standards.
The LVTTL, LVCMOS, SSTL-2 Class I and II, SSTL-18 Class I and II, HSTL-18 Class I
and II, HSTL-15 Class I and II, and HSTL-12 Class I and II I/O standards have several
levels of current strength that you can control.
Chip-Wide Reset
shows the Cyclone III device family IOE structure.
OE
clkout
oe_out
aclr/prn
clkin
oe_in
preset
sclr/
Output Register
OE Register
ENA
ENA
D
D
ACLR
/PRN
ACLR
/PRN
Q
Q
Input Register
ENA
D
ACLR
/PRN
Current Strength Control
Q
Slew Rate Control
Open-Drain Out
Chapter 6: I/O Features in the Cyclone III Device Family
Pin Delay
Output
Input Register
or Input Pin to
Logic Array
Input Pin to
Delay
Delay
V
CCIO
© December 2009 Altera Corporation
V
CCIO
Programmable
I/O Element Features
Resistor
Pull-Up
Bus Hold