EP3C5E144I7N Altera, EP3C5E144I7N Datasheet - Page 259

• Manufacturer Part Number: EP3C5E144I7N
• Description: IC CYCLONE III FPGA 5K 144 EQFP
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C5E144I7N

• Number Of Logic Elements/cells: 5136
• Number Of Labs/clbs: 321
• Total Ram Bits: 423936
• Number Of I /o: 94
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 144-EQFP
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 5136
• # I/os (max): 94
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 5136
• Ram Bits: 423936
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: EQFP
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2557

Chapter 11: SEU Mitigation in the Cyclone III Device Family
Error Detection Timing
Table 11–4. Error Detection Registers
Error Detection Timing
© December 2009
32-bit signature
register
32-bit storage register
Register
Altera Corporation
Table 11–4
When the error detection CRC feature is enabled through the Quartus II software, the
device automatically activates the CRC process upon entering user mode after
configuration and initialization is complete.
The CRC_ERROR pin is driven low until the error detection circuitry has detected a
corrupted bit in the previous CRC calculation. After the pin goes high, it remains high
during the next CRC calculation. This pin does not log the previous CRC calculation.
If the new CRC calculation does not contain any corrupted bits, the CRC_ERROR pin is
driven low. The error detection runs until the device is reset.
The error detection circuitry runs off an internal configuration oscillator with a divisor
that sets the maximum frequency.
Table 11–5
Table 11–5. Minimum and Maximum Error Detection Frequencies
You can set a lower clock frequency by specifying a division factor in the Quartus II
software (for more information, refer to
divisor is a power of two (2), where n is between 0 and 8. The divisor ranges from one
through 256. Refer to
Equation 11–1. Error Detection Frequency
Cyclone III
device family
Device Type
This register contains the CRC signature. The signature register contains the result of the user
mode calculated CRC value compared against the pre-calculated CRC value. If no errors are
detected, the signature register is all zeros. A non-zero signature register indicates an error in the
configuration CRAM contents.
The CRC_ERROR signal is derived from the contents of this register.
This register is loaded with the 32-bit pre-computed CRC signature at the end of the configuration
stage. The signature is then loaded into the 32-bit CRC circuit (called the Compute and Compare
CRC block, as shown in
forms a 32-bit scan chain during execution of the CHANGE_EDREG JTAG instruction. The
CHANGE_EDREG JTAG instruction can change the content of the storage register. Therefore, the
functionality of the error detection CRC circuitry is checked in-system by executing the instruction
to inject an error during the operation. The operation of the device is not halted when issuing the
CHANGE_EDREG instruction.
lists the registers shown in
lists the minimum and maximum error detection frequencies.
Frequency
80 MHz/2
Detection
Error
Equation
Figure
n
Error detection frequency
11–1) during user mode to calculate the CRC error. This register
11–1.
Maximum Error
Frequency
Detection
80 MHz
Figure
Function
“Software Support” on page
11–1.
=
Minimum Error
80 MHz
----------------- -
Frequency
Detection
312.5 kHz
2
n
Cyclone III Device Handbook, Volume 1
0, 1, 2, 3, 4, 5, 6, 7, 8
Valid Divisors (2
11–6). The
11–5
ν
)