EP3C5E144I7N Altera, EP3C5E144I7N Datasheet - Page 188

• Manufacturer Part Number: EP3C5E144I7N
• Description: IC CYCLONE III FPGA 5K 144 EQFP
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C5E144I7N

• Number Of Logic Elements/cells: 5136
• Number Of Labs/clbs: 321
• Total Ram Bits: 423936
• Number Of I /o: 94
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 144-EQFP
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 5136
• # I/os (max): 94
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 5136
• Ram Bits: 423936
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: EQFP
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2557

9–28
Figure 9–9. Byte-Wide Multi-Device AP Configuration
Notes to
(1) Connect the pull-up resistors to the V
(2) Connect the pull-up resistor to the V
(3) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. You must set the master device in AP mode and the slave
(5) The AP configuration ignores the WAIT signal during configuration mode. However, if you are accessing flash during user mode with user logic,
(6) Connect the repeater buffers between the master device and slave devices for DATA[15..0] and DCLK. All I/O inputs must maintain a
Cyclone III Device Handbook, Volume 1
devices in FPP mode. To connect MSEL[3..0] for the master device in AP mode and the slave devices in FPP mode, refer to
page
you can optionally use the normal I/O to monitor the WAIT signal from the Numonyx P30 or P33 flash.
maximum AC voltage of 4.1 V. The output resistance of the repeater buffers must fit the maximum overshoot equation outlined in
and JTAG Pin I/O Requirements” on page
Numonyx P30/P33 Flash
Figure
9–11. Connect the MSEL pins directly to V
9–9:
DQ[15:0]
A[24:1]
RST#
ADV#
WAIT
WE#
OE#
CLK
CE#
Byte-Wide Multi-Device AP Configuration
The simpler method for multi-device AP configuration is the byte-wide multi-device
AP configuration. In the byte-wide multi-device AP configuration, the LSB of the
DATA[7..0]pin from the flash and master device (set to the AP configuration
scheme) is connected to the slave devices set to the FPP configuration scheme, as
shown in
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
GND
CCIO
10
Figure
CCIO
V CCIO (1)
kΩ
Buffers (6)
supply voltage of the I/O bank in which the nCE pin resides.
Cyclone III Master Device
nCE
DCLK
nRESET
FLASH_nCE
nOE
nAVD
nWE
I/O (5)
DATA[15..0]
PADD[23..0]
supply of the bank in which the pin resides.
9–7.
10
9–9.
V CCIO (1)
kΩ
CCA
or GND.
MSEL[3..0]
10
V CCIO (1)
kΩ
nCEO
10
V CCIO (2)
kΩ
DQ[7..0]
(4)
nCE
DATA[7..0]
DCLK
Cyclone III Slave Device
MSEL[3..0]
nCEO
10
V CCIO (2)
kΩ
DQ[7..0]
(4)
© December 2009 Altera Corporation
nCE
DATA[7..0]
DCLK
Cyclone III Slave Device
MSEL[3..0]
Configuration Features
nCEO
Table 9–7 on
“Configuration
(4)
N.C. (3)