EP3C5E144I7N Altera, EP3C5E144I7N Datasheet - Page 258

• Manufacturer Part Number: EP3C5E144I7N
• Description: IC CYCLONE III FPGA 5K 144 EQFP
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C5E144I7N

• Number Of Logic Elements/cells: 5136
• Number Of Labs/clbs: 321
• Total Ram Bits: 423936
• Number Of I /o: 94
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 144-EQFP
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 5136
• # I/os (max): 94
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 5136
• Ram Bits: 423936
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: EQFP
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2557

11–4
Error Detection Block
Table 11–3. Types of CRC Detection to Check the Configuration Bits
Error Detection Registers
Cyclone III Device Handbook, Volume 1
■
■
CRAM error checking ability (32-bit CRC)
during user mode, for use by the
CRC_ERROR pin.
There is only one 32-bit CRC value, and
this value covers all the CRAM data.
First Type of CRC Detection
f
1
For more information about the CRC_ERROR pin information for Cyclone III device
family, refer to the
WYSIWYG is an optimization technique that performs optimization on VQM (Verilog
Quartus Mapping) netlist in the Quartus II software.
Table 11–3
This section focuses on the first type—the 32-bit CRC when the device is in user
mode.
There are two sets of 32-bit registers in the error detection circuitry that store the
computed CRC signature and pre-calculated CRC value. A non-zero value on the
signature register causes the CRC_ERROR pin to set high.
Figure 11–1
32-bit registers: the signature register and the storage register.
Figure 11–1. Error Detection Block Diagram
lists the types of CRC detection to check the configuration bits.
Error Detection
State Machine
32-bit Storage
shows the block diagram of the error detection block and the two related
Register
Cyclone III Devices Pin-Outs
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■
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■
16-bit CRC embedded in every configuration data frame.
During configuration, after a frame of data is loaded into the device, the
pre-computed CRC is shifted into the CRC circuitry.
Simultaneously, the CRC value for the data frame shifted-in is calculated.
If the pre-computed CRC and calculated CRC values do not match,
nSTATUS is set low.
Every data frame has a 16-bit CRC. Therefore, there are many 16-bit CRC
values for the whole configuration bit stream.
Every device has a different length of configuration data frame.
32
Control Signals
Second Type of CRC Detection
Chapter 11: SEU Mitigation in the Cyclone III Device Family
on the Altera
Compute & Compare
32-bit Signature
Register
CRC
© December 2009 Altera Corporation
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32
®
website.
Error Detection Block