EP3C5E144I7N Altera, EP3C5E144I7N Datasheet - Page 244

IC CYCLONE III FPGA 5K 144 EQFP

EP3C5E144I7N

Manufacturer Part Number
EP3C5E144I7N
Description
IC CYCLONE III FPGA 5K 144 EQFP
Manufacturer
Altera
Series
Cyclone® IIIr

Specifications of EP3C5E144I7N

Number Of Logic Elements/cells
5136
Number Of Labs/clbs
321
Total Ram Bits
423936
Number Of I /o
94
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
144-EQFP
Family Name
Cyclone III
Number Of Logic Blocks/elements
5136
# I/os (max)
94
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
5136
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
EQFP
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2557

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9–84
Table 9–27. Remote System Upgrade Control Register Contents
Cyclone III Device Handbook, Volume 1
Wd_timer[11..0]
Ru_address[21..0] 22'b0000000000000000000000
Rsv1
Wd_en
Osc_int
Cd_early
Rsv2
Note to
(1) Option bit for the application configuration.
Control Register Bit
Table
(1)
9–27:
(1)
1
Figure 9–36. Remote System Upgrade Control Register
When enabled, the early CONF_DONE check (Cd_early) option bit ensures that there
is a valid configuration at the boot address specified by the factory configuration and
that it is of the proper size. If an invalid configuration is detected or CONF_DONE pin is
asserted too early, the device resets and then reconfigures the factory configuration
image. The internal oscillator, as startup state machine clock (Osc_int) option bit,
ensures a functional startup clock to eliminate the hanging of startup when enabled.
When all option bits are turned on, they provide complete coverage for the
programming and startup portions of the application configuration. It is strongly
recommended that you turn on both the Cd_early and Osc_int option bits.
The Cd_early and Osc_int option bits for the application configuration must be
turned on by the factory configuration.
Remote System Upgrade Status Register
The remote system upgrade status register specifies the reconfiguration trigger
condition. The various trigger and error conditions include:
Cyclical redundancy check (CRC) error during application configuration
nSTATUS assertion by an external device due to an error
Cyclone III device family logic array triggered a reconfiguration cycle, possibly
after downloading a new application configuration image
12'b000000000000
1'b0
1'b1
1’b1
1’b1
1'b1
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Rsv2
38
Cd_early Osc_int Wd_en Rsv1 Ru_address[21..0] Wd_timer[11..0]
Value
37
36
35
User watchdog time-out value (most significant 12 bits of
29-bit count value:
{Wd_timer[11..0],17'b1000})
Configuration address (most significant 22 bits of 24-bit
boot address value:
boot_address[23:0] =
{Ru_address[21..0],2'b0})
Reserved bit
User watchdog timer enable bit
Internal oscillator as startup state machine clock enable bit
Early CONF_DONE check
Reserved bit
34 33
Definition
© December 2009 Altera Corporation
12 11
Remote System Upgrade
0

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