XC3S400-4PQ208C Xilinx Inc, XC3S400-4PQ208C Datasheet - Page 81

• Manufacturer Part Number: XC3S400-4PQ208C
• Description: IC SPARTAN-3 FPGA 400K 208PQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S400-4PQ208C

• Number Of Logic Elements/cells: 8064
• Number Of Labs/clbs: 896
• Total Ram Bits: 294912
• Number Of I /o: 141
• Number Of Gates: 400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Other names: Q2844431; XC3S4004PQ208C; XC3S4004PQ208C

Table 49: Recommended Number of Simultaneously
Switching Outputs per V
DS099-3 (v2.5) December 4, 2009
Product Specification
98
LVCMOS33
LVDCI_33
LVDCI_DV2_33
HSLVDCI_33
LVTTL
Signal Standard
(IOSTANDARD)
R
Slow
Slow
Fast
Fast
12
16
24
12
16
24
12
16
24
12
16
24
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
100
VQ
34
17
17
10
20
15
11
10
10
10
10
34
17
17
12
10
10
20
13
11
10
9
8
8
8
8
7
8
9
8
7
CCO
-GND Pair (Continued)
144
TQ
25
16
15
12
10
10
13
11
10
24
14
11
10
20
15
11
10
10
10
10
20
9
8
8
8
8
7
8
9
8
7
Package
208
PQ
24
14
11
10
20
15
11
10
10
10
10
25
16
15
12
10
10
20
13
11
10
9
8
8
8
8
7
8
9
8
7
132
CP
Spartan-3 FPGA Family: DC and Switching Characteristics
52
26
26
13
13
26
15
13
10
10
10
10
52
26
26
13
13
10
26
13
13
10
8
8
8
8
7
8
9
8
7
FG1156
FG320,
FG456,
FG676,
FG900,
FT256,
76
46
27
20
13
10
44
26
16
12
10
10
10
10
60
41
29
22
13
11
34
20
15
12
10
www.xilinx.com
9
8
7
9
9
7
Table 49: Recommended Number of Simultaneously
Switching Outputs per V
Notes:
1.
2.
3.
4.
PCI33_3
SSTL18_I
SSTL18_I_DCI
SSTL18_II
SSTL2_I
SSTL2_I_DCI
SSTL2_II
SSTL2_II_DCI
Differential Standards (Number of I/O Pairs or Channels)
LDT_25 (ULVDS_25)
LVDS_25
BLVDS_25
LVDSEXT_25
LVPECL_25
RSDS_25
DIFF_HSTL_II_18
DIFF_HSTL_II_18_DCI
DIFF_SSTL2_II
DIFF_SSTL2_II_DCI
Signal Standard
The numbers in this table are recommendations that assume the
FPGA is soldered on a printed circuit board using sound practices.
This table assumes the following parasitic factors: combined PCB
trace and land inductance per V
capacitive load of 15 pF. Test limits are the V
the respective I/O standard.
Regarding the SSO numbers for all DCI standards, the R
connected to the V
If more than one signal standard is assigned to the I/Os of a given
bank, refer to XAPP689: "Managing Ground Bounce in Large
FPGAs" for information on how to perform weighted average SSO
calculations.
Results are based on actual silicon testing using an FPGA soldered
on a typical printed-circuit board.
(IOSTANDARD)
RN
and V
100
VQ
13
13
10
10
9
8
6
6
5
7
2
5
2
7
4
4
3
3
CCO
RP
pins of the FPGA are 50Ω.
CCO
-GND Pair (Continued)
144
TQ
13
13
10
10
9
8
6
6
5
5
1
5
1
5
4
4
3
3
and GND pin of 1.0 nH, receiver
Package
208
PQ
13
13
10
10
9
8
6
6
5
5
1
5
1
5
4
4
3
3
IL
/V
IH
132
voltage limits for
CP
13
13
10
10
12
12
9
8
6
6
5
5
4
4
3
3
REF
FG1156
FG320,
FG456,
FG676,
FG900,
FT256,
resistors
17
17
13
13
20
20
4
4
4
4
9
9
9
9
5
4
5
4
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