XC3S400-4PQ208C Xilinx Inc, XC3S400-4PQ208C Datasheet - Page 147

• Manufacturer Part Number: XC3S400-4PQ208C
• Description: IC SPARTAN-3 FPGA 400K 208PQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S400-4PQ208C

• Number Of Logic Elements/cells: 8064
• Number Of Labs/clbs: 896
• Total Ram Bits: 294912
• Number Of I /o: 141
• Number Of Gates: 400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Other names: Q2844431; XC3S4004PQ208C; XC3S4004PQ208C

FG320: 320-lead Fine-pitch Ball Grid
Array
The 320-lead fine-pitch ball grid array package, FG320,
supports three different Spartan-3 devices, including the
XC3S400, the XC3S1000, and the XC3S1500. The footprint
for all three devices is identical, as shown in
Figure
The FG320 package is an 18 x 18 array of solder balls
minus the four center balls.
All the package pins appear in
bank number, then by pin name. Pairs of pins that form a dif-
ferential I/O pair appear together in the table. The table also
shows the pin number for each pin and the pin type, as
defined earlier.
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web-
site at
sheets/s3_pin.zip
Pinout Table
Table 97: FG320 Package Pinout
DS099-4 (v2.5) December 4, 2009
Product Specification
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
47.
http://www.xilinx.com/support/documentation/data_
IO
IO
IO/VREF_0
IO/VREF_0
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L09N_0
IO_L09P_0
IO_L10N_0
IO_L10P_0
IO_L15N_0
IO_L15P_0
IO_L25N_0
IO_L25P_0
IO_L27N_0
IO_L27P_0
IO_L28N_0
IO_L28P_0
IO_L29N_0
IO_L29P_0
IO_L30N_0
IO_L30P_0
IO_L31N_0
IO_L31P_0/VREF_0
R
.
XC3S1000
XC3S1500
Pin Name
XC3S400
Table 97
Number
FG320
Pin
D9
E7
B3
D6
A2
A3
B4
C4
C5
D5
A4
A5
B5
B6
C7
D7
C8
D8
E8
A7
A8
B9
A9
F8
and are sorted by
Table 97
VREF
VREF
VREF
Type
DCI
DCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
www.xilinx.com
and
Table 97: FG320 Package Pinout (Continued)
Bank
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
Spartan-3 FPGA Family: Pinout Descriptions
IO_L32N_0/GCLK7
IO_L32P_0/GCLK6
VCCO_0
VCCO_0
VCCO_0
VCCO_0
IO
IO
IO
IO/VREF_1
IO_L01N_1/VRP_1
IO_L01P_1/VRN_1
IO_L10N_1/VREF_1
IO_L10P_1
IO_L15N_1
IO_L15P_1
IO_L16N_1
IO_L16P_1
IO_L24N_1
IO_L24P_1
IO_L27N_1
IO_L27P_1
IO_L28N_1
IO_L28P_1
IO_L29N_1
IO_L29P_1
IO_L30N_1
IO_L30P_1
IO_L31N_1/VREF_1
IO_L31P_1
IO_L32N_1/GCLK5
IO_L32P_1/GCLK4
VCCO_1
VCCO_1
VCCO_1
VCCO_1
IO
IO_L01N_2/VRP_2
IO_L01P_2/VRN_2
IO_L16N_2
IO_L16P_2
IO_L17N_2
IO_L17P_2/VREF_2
XC3S1000
XC3S1500
Pin Name
XC3S400
Number
FG320
A11
B13
D10
A12
A16
A17
A15
B15
C14
C15
A14
B14
D14
D13
E13
E12
C12
D12
E11
C11
D11
A10
B10
E10
B11
C13
G10
G11
C16
C17
B18
C18
D17
D18
Pin
F11
F10
J13
E9
B8
C6
G8
G9
F9
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
GCLK
GCLK
VREF
VREF
VREF
GCLK
GCLK
VREF
Type
DCI
DCI
DCI
DCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
147