XC3S400-4PQ208C Xilinx Inc, XC3S400-4PQ208C Datasheet - Page 31

• Manufacturer Part Number: XC3S400-4PQ208C
• Description: IC SPARTAN-3 FPGA 400K 208PQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S400-4PQ208C

• Number Of Logic Elements/cells: 8064
• Number Of Labs/clbs: 896
• Total Ram Bits: 294912
• Number Of I /o: 141
• Number Of Gates: 400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Other names: Q2844431; XC3S4004PQ208C; XC3S4004PQ208C

Table 14: Embedded Multiplier Primitives Descriptions
Digital Clock Manager (DCM)
Spartan-3 devices provide flexible, complete control over
clock frequency, phase shift and skew through the use of
the DCM feature. To accomplish this, the DCM employs a
Delay-Locked Loop (DLL), a fully digital control system that
uses feedback to maintain clock signal characteristics with a
high degree of precision despite normal variations in oper-
ating temperature and voltage. This section provides a fun-
damental description of the DCM. For further information,
refer to the “Using Digital Clock Managers” chapter in
UG331.
Each member of the Spartan-3 family has four DCMs,
except the smallest, the XC3S50, which has two DCMs.
The DCMs are located at the ends of the outermost Block
RAM column(s). See
Manager is placed in a design as the “DCM” primitive.
The DCM supports three major functions:
•
DS099-2 (v2.5) December 4, 2009
Product Specification
Notes:
1.
A[17:0]
B[17:0]
P[35:0]
CLK
CE
RST
Signal
Name
Clock-skew Elimination: Clock skew describes the
extent to which clock signals may, under normal
circumstances, deviate from zero-phase alignment. It
occurs when slight differences in path delays cause the
The control signals CLK, CE and RST have the option of inverted polarity.
R
Direction
Output
Input
Input
Input
Input
Input
Figure 1, page
Apply one 18-bit multiplicand to these inputs. The MULT18X18S primitive requires a setup time
before the enabled rising edge of CLK.
Apply the other 18-bit multiplicand to these inputs. The MULT18X18S primitive requires a setup
time before the enabled rising edge of CLK.
The output on the P bus is a 36-bit product of the multiplicands A and B. In the case of the
MULT18X18S primitive, an enabled rising CLK edge updates the P bus.
CLK is only an input to the MULT18X18S primitive. The clock signal applied to this input when
enabled by CE, updates the output register that drives the P bus.
CE is only an input to the MULT18X18S primitive. Enable for the CLK signal. Asserting this input
enables the CLK signal to update the P bus.
RST is only an input to the MULT18X18S primitive. Asserting this input resets the output register
on an enabled, rising CLK edge, forcing the P bus to all zeroes.
4. The Digital Clock
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clock signal to arrive at different points on the die at
different times. This clock skew can increase set-up
and hold time requirements as well as clock-to-out
time, which may be undesirable in applications
operating at a high frequency, when timing is critical.
The DCM eliminates clock skew by aligning the output
clock signal it generates with another version of the
clock signal that is fed back. As a result, the two clock
signals establish a zero-phase relationship. This
effectively cancels out clock distribution delays that
may lie in the signal path leading from the clock output
of the DCM to its feedback input.
Frequency Synthesis: Provided with an input clock
signal, the DCM can generate a wide range of different
output clock frequencies. This is accomplished by
either multiplying and/or dividing the frequency of the
input clock signal by any of several different factors.
Phase Shifting: The DCM provides the ability to shift
the phase of all its output clock signals with respect to
its input clock signal.
Function
Spartan-3 FPGA Family: Functional Description
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