XC3S400-4PQ208C Xilinx Inc, XC3S400-4PQ208C Datasheet - Page 49

• Manufacturer Part Number: XC3S400-4PQ208C
• Description: IC SPARTAN-3 FPGA 400K 208PQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S400-4PQ208C

• Number Of Logic Elements/cells: 8064
• Number Of Labs/clbs: 896
• Total Ram Bits: 294912
• Number Of I /o: 141
• Number Of Gates: 400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Other names: Q2844431; XC3S4004PQ208C; XC3S4004PQ208C

Master Parallel Mode
In this mode, the FPGA configures from byte-wide data, and
the FPGA supplies the CCLK configuration clock. In Master
configuration modes, CCLK behaves as a bidirectional I/O
pin. Timing is similar to the Slave Parallel mode except that
CCLK is supplied by the FPGA. The device connections are
shown in
Boundary-Scan (JTAG) Mode
In Boundary-Scan mode, dedicated pins are used for con-
figuring the FPGA. The configuration is done entirely
through the IEEE 1149.1 Test Access Port (TAP). FPGA
configuration using the Boundary-Scan mode is compatible
with the IEEE Std 1149.1-1993 standard and IEEE Std
1532 for In-System Configurable (ISC) devices.
Configuration through the boundary-scan port is always
available, regardless of the selected configuration mode. In
some cases, however, the mode pin setting may affect
proper programming of the device due to various interac-
tions. For example, if the mode pins are set to Master Serial
DS099-2 (v2.5) December 4, 2009
Product Specification
Figure
R
Notes:
1.
26.
There are two ways to use the DONE line. First, one may set the BitGen option DriveDone to "Yes"
only for the last FPGA to be configured in the chain shown above (or for the single FPGA as may be
the case). This enables the DONE pin to drive High; thus, no pull-up resistor is necessary. DriveDone
is set to "No" for the remaining FPGAs in the chain. Second, DriveDone can be set to "No" for all
FPGAs. Then all DONE lines are open-drain and require the pull-up resistor shown in grey. In most
cases, a value between 3.3KΩ to 4.7KΩ is sufficient. However, when using DONE synchronously
with a long chain of FPGAs, cumulative capacitance may necessitate lower resistor values (e.g.
down to 330Ω) in order to ensure a rise time within one clock cycle.
Figure 26: Connection Diagram for Master Parallel Configuration
1.8V
V
Platform Flash
CCINT
XCFxxP
PROM
V
GND
CCO
OE/RESET
DATA[0:7]
CCLK
V
CF
CE
CCJ
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2.5V
2.5V
or Master Parallel mode, and the associated PROM is
already programmed with a valid configuration image, then
there is potential for configuration interference between the
JTAG and PROM data. Selecting the Boundary-Scan mode
disables the other modes and is the most reliable mode
when programming via JTAG.
Configuration Sequence
The configuration of Spartan-3 devices is a three-stage pro-
cess that occurs after Power-On Reset or the assertion of
PROG_B. POR occurs after the V
Bank 4 supplies have reached their respective maximum
input threshold levels (see
the three-stage process begins.
First, the configuration memory is cleared. Next, con-
figuration data is loaded into the memory, and finally, the
logic is activated by a start-up process. A flow diagram for
the configuration sequence of the Serial and Parallel modes
is shown in
ary-Scan configuration sequence appears in
4.7KΩ
All
2.5V
Spartan-3 FPGA Family: Functional Description
V
D[0:7]
CCLK
RDWR_B
V
PROG_B
DONE
INIT_B
CS_B
CCAUX
CCO
Spartan-3
Figure
Master
Banks 4 & 5
GND
DS099_25_112905
V
CCINT
27. The flow diagram for the Bound-
1.2V
Table 28, page
CCINT
, V
CCAUX
56). After POR,
Figure
, and V
28.
CCO
49