CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet - Page 19

• Manufacturer Part Number: CY7C67300-100AXI
• Description: IC USB HOST/PERIPH CNTRL 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r
• Type: Host Programmable Embedded USBr

Specifications of CY7C67300-100AXI

• Package / Case: 100-LQFP
• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1865; CY7C67300-100AXI

Power Control Register [0xC00A] [R/W]
Table 28. Power Control Register
Register Description
The Power Control register controls the power down and wakeup
options. Either the sleep mode or the halt mode options can be
selected. All other writable bits in this register can be used as a
wakeup source while in sleep mode.
Host/Device 2B Wake Enable (Bit 15)
The Host/Device 2B Wake Enable bit enables or disables a
wakeup condition to occur on a Host/Device 2B transition. This
wakeup from the SIE port does not cause an interrupt to the
on-chip CPU.
1: Enable wakeup on Host/Device 2B transition
0: Disable wakeup on Host/Device 2B transition
Host/Device 2A Wake Enable (Bit 14)
The Host/Device 2A Wake Enable bit enables or disables a
wakeup condition to occur on an Host/Device 2A transition. This
wakeup from the SIE port does not cause an interrupt to the
on-chip CPU.
1: Enable wakeup on Host/Device 2A transition
0: Disable wakeup on Host/Device 2A transition
Host/Device 1B Wake Enable (Bit 13)
The Host/Device 1B Wake Enable bit enables or disables a
wakeup condition to occur on an Host/Device 1B transition. This
wakeup from the SIE port does not cause an interrupt to the
on-chip CPU.
1: Enable wakeup on Host/Device 1B transition
0: Disable wakeup on Host/Device 1B transition
Host/Device 1A Wake Enable (Bit 12)
The Host/Device 1A Wake Enable bit enables or disables a
wakeup condition to occur on an Host/Device 1A transition. This
wakeup from the SIE port does not cause an interrupt to the
on-chip CPU.
1: Enable wakeup on Host/Device 1A transition
0: Disable wakeup on Host/Device 1A transition
Document #: 38-08015 Rev. *J
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Host/Device
Enable
Enable
Wake
Wake
R/W
R/W
HPI
15
2B
0
7
0
Host/Device
Enable
Wake
R/W
14
2A
0
6
0
-
Reserved
Host/Device
Enable
Wake
R/W
13
1B
0
5
0
-
Host/Device
Enable
Enable
Wake
Wake
R/W
R/W
GPI
12
1A
0
4
0
OTG Wake Enable (Bit 11)
The OTG Wake Enable bit enables or disables a wakeup
condition to occur on either an OTG VBUS_Valid or OTG ID
transition (IRQ20).
1: Enable wakeup on OTG VBUS valid or OTG ID transition
0: Disable wakeup on OTG VBUS valid or OTG ID transition
HSS Wake Enable (Bit 9)
The HSS Wake Enable bit enables or disables a wakeup
condition to occur on an HSS Rx serial input transition. The
processor may take several hundreds of microseconds before
being operational after wakeup. Therefore, the incoming data
byte that causes the wakeup is discarded.
1: Enable wakeup on HSS Rx serial input transition
0: Disable wakeup on HSS Rx serial input transition
SPI Wake Enable (Bit 8)
The SPI Wake Enable bit enables or disables a wakeup condition
to occur on a falling SPI_nSS input transition. The processor
may take several hundreds of microseconds before being opera-
tional after wakeup. Therefore, the incoming data byte that
causes the wakeup is discarded.
1: Enable wakeup on falling SPI nSS input transition
0: Disable SPI_nSS interrupt
HPI Wake Enable (Bit 7)
The HPI Wake Enable bit enables or disables a wakeup
condition to occur on an HPI interface read.
1: Enable wakeup on HPI interface read
0: Disable wakeup on HPI interface read
GPI Wake Enable (Bit 4)
The GPI Wake Enable bit enables or disables a wakeup
condition to occur on a GPIO(25:24) transition.
1: Enable wakeup on GPIO(25:24) transition
0: Disable wakeup on GPIO(25:24) transition
Reserved
Enable
Wake
OTG
R/W
11
3
0
0
-
Reserved
Boost 3V
OK
10
R
2
0
0
-
Enable
Enable
Sleep
Wake
HSS
R/W
R/W
1
0
9
0
CY7C67300
Enable
Enable
Page 19 of 99
Wake
R/W
R/W
Halt
SPI
0
0
8
0
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