CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet - Page 2

• Manufacturer Part Number: CY7C67300-100AXI
• Description: IC USB HOST/PERIPH CNTRL 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r
• Type: Host Programmable Embedded USBr

Specifications of CY7C67300-100AXI

• Package / Case: 100-LQFP
• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1865; CY7C67300-100AXI

Introduction
EZ-Host™ (CY7C67300) is Cypress Semiconductor’s first
full-speed, low cost multiport host/peripheral controller. EZ-Host
is designed to easily interface to most high performance CPUs
to add USB host functionality. EZ-Host has its own 16-bit RISC
processor to act as a coprocessor or operate in standalone
mode. EZ-Host also has a programmable IO interface block
allowing a wide range of interface options.
Functional Overview
An overview of the processor core components are presented in
this section.
Processor Core
EZ-Host has a general purpose 16-bit embedded RISC
processor that runs at 48 MHz.
Clocking
EZ-Host requires a 12 MHz source for clocking. Either an
external crystal or TTL level oscillator may be used. EZ-Host has
an internal PLL that produces a 48 MHz internal clock from the
12 MHz source.
Memory
EZ-Host has a built in 4K × 16 masked ROM and an 8K × 16
internal RAM. The masked ROM contains the EZ-Host BIOS.
The internal RAM can be used for program code or data.
Table 1. Interface Options for GPIO Pins
Document #: 38-08015 Rev. *J
Note
1. Default interface location.
GPIO Pins
GPIO31
GPIO30
GPIO29
GPIO28
GPIO27
GPIO26
GPIO25
GPIO24
GPIO23
GPIO22
GPIO21
GPIO20
GPIO19
GPIO18
GPIO17
GPIO16
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
nWR
nRD
nCS
D15
D14
D13
D12
HPI
D11
INT
A1
A0
IOREADY
IOW
CS1
CS0
IOR
D15
D14
D13
D12
IDE
D11
A2
A1
A0
PWM3
PWM2
PWM1
PWM0
PWM
RXD
CTS
RTS
TXD
HSS
[1]
[1]
[1]
[1]
Interrupts
EZ-Host provides 128 interrupt vectors. The first 48 vectors are
hardware interrupts and the following 80 vectors are software
interrupts.
General Timers and Watchdog Timer
EZ-Host has two built in programmable timers and a Watchdog
timer. All three timers can generate an interrupt to the EZ-Host.
Power Management
EZ-Host has one main power saving mode, Sleep. Sleep mode
pauses all operations and provides the lowest power state.
Interface Descriptions
EZ-Host has a wide variety of interface options for connectivity.
With several interface options available, EZ-Host can act as a
seamless data transport between many different types of
devices.
See
faces share pins and which can coexist. Note that some inter-
faces have more then one possible port location selectable
through the GPIO control register [0xC006]. General guidelines
for interfaces are as follows:
■
■
■
HPI and IDE interfaces are mutually exclusive.
If 16-bit external memory is required, then HSS and SPI default
locations must be used.
I
2
C EEPROM and OTG do not conflict with any interfaces.
Table 1
MOSI
SPI
[1]
and
Table 2 on page 3
UART
RX
TX
SCL/SDA
SCL/SDA
to understand how the inter-
I2C
CY7C67300
OTGID
OTG
Page 2 of 99
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