CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet - Page 30

• Manufacturer Part Number: CY7C67300-100AXI
• Description: IC USB HOST/PERIPH CNTRL 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r
• Type: Host Programmable Embedded USBr

Specifications of CY7C67300-100AXI

• Package / Case: 100-LQFP
• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1865; CY7C67300-100AXI

Sequence Select (Bit 6)
The Sequence Select bit sets the data toggle for the next packet.
This bit has no effect on receiving data packets; sequence
checking must be handled in firmware.
1: Send DATA1
0: Send DATA0
Sync Enable (Bit 5)
The Sync Enable bit synchronizes the transfer with the SOF
packet in full-speed mode and the EOP packet in low-speed
mode.
1: The next enabled packet is transferred after the SOF or EOP
packet is transmitted
0: The next enabled packet is transferred as soon as the SIE is
free
Host n Address Register [R/W]
■
■
Table 49. Host n Address Register
Register Description
The Host n Address register is used as the base pointer into
memory space for the current host transactions.
Host n Count Register [R/W]
■
■
Table 50. Host n Count Register
Document #: 38-08015 Rev. *J
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Host 1 Address Register 0xC082
Host 2 Address Register 0xC0A2
Host 1 Count Register 0xC084.
Host 2 Count Register 0xC0A4.
Reserved
R/W
R/W
R/W
15
15
0
7
0
0
7
0
-
Select
R/W
R/W
R/W
Port
R/W
14
14
0
6
0
0
6
0
R/W
R/W
R/W
13
13
0
5
0
0
5
0
-
R/W
R/W
R/W
12
12
0
4
0
0
4
0
-
Address...
...Address
Reserved
...Count
ISO Enable (Bit 4)
The ISO Enable bit enables or disables an isochronous trans-
action.
1: Enable isochronous transaction
0: Disable isochronous transaction
Arm Enable (Bit 0)
The Arm Enable bit arms an endpoint and starts a transaction.
This bit is automatically cleared to ‘0’ when a transaction is
complete.
1: Arm endpoint and begin transaction
0: Endpoint disarmed
Reserved
Write all reserved bits with ’0’.
Address (Bits [15:0])
The Address field sets the address pointer into internal RAM or
ROM.
R/W
R/W
R/W
11
11
0
0
3
0
3
0
-
R/W
R/W
R/W
10
10
0
0
2
0
-
2
0
R/W
R/W
R/W
R/W
9
0
9
0
1
0
1
0
Count...
CY7C67300
Page 30 of 99
R/W
R/W
R/W
R/W
8
0
8
0
0
0
0
0
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