CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet - Page 21

• Manufacturer Part Number: CY7C67300-100AXI
• Description: IC USB HOST/PERIPH CNTRL 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r
• Type: Host Programmable Embedded USBr

Specifications of CY7C67300-100AXI

• Package / Case: 100-LQFP
• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1865; CY7C67300-100AXI

HSS Interrupt Enable (Bit 7)
The HSS Interrupt Enable bit enables or disables the following
High-speed Serial Interface hardware interrupts: HSS Block
Done and HSS RX Full.
1: Enable HSS interrupt
0: Disable HSS interrupt
In Mailbox Interrupt Enable (Bit 6)
The In Mailbox Interrupt Enable bit enables or disables the HPI:
Incoming Mailbox hardware interrupt.
1: Enable MBXI interrupt
0: Disable MBXI interrupt
Out Mailbox Interrupt Enable (Bit 5)
The Out Mailbox Interrupt Enable bit enables or disables the HPI:
Outgoing Mailbox hardware interrupt.
1: Enable MBXO interrupt
0: Disable MBXO interrupt
UART Interrupt Enable (Bit 3)
The UART Interrupt Enable bit enables or disables the following
UART hardware interrupts: UART TX, and UART RX.
1: Enable UART interrupt
0: Disable UART interrupt
Breakpoint Register [0xC014] [R/W]
Table 30. Breakpoint Register
Register Description
The Breakpoint register holds the breakpoint address. When the
program counter matches this address, the INT127 interrupt
occurs. To clear this interrupt, write a zero value to this register.
Document #: 38-08015 Rev. *J
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
R/W
R/W
15
0
7
0
R/W
R/W
14
0
6
0
R/W
R/W
13
0
5
0
R/W
R/W
12
0
4
0
Address...
...Address
GPIO Interrupt Enable (Bit 2)
The GPIO Interrupt Enable bit enables or disables the General
Purpose IO pins interrupt (see the
[0xC006] [R/W] on page
pending GPIO interrupts are also cleared
1: Enable GPIO interrupt
0: Disable GPIO interrupt
Timer 1 Interrupt Enable (Bit 1)
The Timer 1 Interrupt Enable bit enables or disables the TImer1
Interrupt Enable. When this bit is reset, all pending Timer 1 inter-
rupts are cleared.
1: Enable TM1 interrupt
0: Disable TM1 interrupt
Timer 0 Interrupt Enable (Bit 0)
The Timer 0 Interrupt Enable bit enables or disables the TImer0
Interrupt Enable. When this bit is reset, all pending Timer 0 inter-
rupts are cleared.
1: Enable TM0 interrupt
0: Disable TM0 interrupt
Reserved
Write all reserved bits with ’0’.
Address (Bits [15:0])
The Address field is a 16-bit field containing the breakpoint
address.
R/W
R/W
11
0
3
0
R/W
R/W
10
0
2
0
50). When the GPIO bit is reset, all
R/W
R/W
9
0
1
0
GPIO Control Register
CY7C67300
Page 21 of 99
R/W
R/W
8
0
0
0
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