CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet - Page 65

• Manufacturer Part Number: CY7C67300-100AXI
• Description: IC USB HOST/PERIPH CNTRL 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r
• Type: Host Programmable Embedded USBr

Specifications of CY7C67300-100AXI

• Package / Case: 100-LQFP
• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1865; CY7C67300-100AXI

Done1 Flag (Bit 2)
In host mode the Done 1 Flag bit is a read only bit that indicates
if a host packet done interrupt occurs on Host 1. In device mode
this read only bit indicates if an any of the endpoint interrupts
occur on Device 1. Firmware needs to determine which endpoint
interrupt occurred.
1: Interrupt triggered
0: Interrupt did not trigger
Reset1 Flag (Bit 1)
SPI Registers
There are twelve registers dedicated to SPI operation. Each of these registers is covered in this section and summarized in
Table 104. SPI Registers
Document #: 38-08015 Rev. *J
SPI Configuration Register
SPI Control Register
SPI Interrupt Enable Register
SPI Status Register
SPI Interrupt Clear Register
SPI CRC Control Register
SPI CRC Value
SPI Data Register
SPI Transmit Address Register
SPI Transmit Count Register
SPI Receive Address Register
SPI Receive Count Register
Register Name
The Reset1 Flag bit is a read only bit that indicates if a USB
Reset interrupt occurs on either Host/Device 1.
1: Interrupt triggered
0: Interrupt did not trigger
Mailbox Out Flag (Bit 0)
The Mailbox Out Flag bit is a read only bit that indicates if a
message is ready in the outgoing mailbox. This interrupt clears
when the external host reads from the HPI Mailbox register.
1: Interrupt triggered
0: Interrupt did not trigger
0xC0C8
0xC0CA
0xC0CC
0xC0D0
0xC0D2
0xC0D8
0xC0DA
0xC0DC
0xC0DE
0xC0CE
0xC0D4
0xC0D6
Address
R/W
R/W
R/W
R
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CY7C67300
R/W
Page 65 of 99
Table
104.
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