CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet - Page 38

• Manufacturer Part Number: CY7C67300-100AXI
• Description: IC USB HOST/PERIPH CNTRL 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r
• Type: Host Programmable Embedded USBr

Specifications of CY7C67300-100AXI

• Package / Case: 100-LQFP
• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1865; CY7C67300-100AXI

USB Device Only Registers
There are eleven sets of USB Device Only registers. All sets consist of at least two registers, one for Device Port 1 and one for Device
Port 2. In addition, each Device port has eight possible endpoints. This gives each endpoint register set eight registers for each Device
Port for a total of sixteen registers per set. The USB Device Only registers are covered in this section and summarized in
Table 62. USB Device Only Registers
Device n Endpoint n Control Register [R/W]
■
■
■
■
■
■
■
■
Table 63. Device n Endpoint n Control Register
Register Description
The Device n Endpoint n Control register provides control over a
single EP in device mode. There are a total of eight endpoints for
each of the two ports. All endpoints have the same definition for
their Device n Endpoint n Control register.
Document #: 38-08015 Rev. *J
Register Name
Device n Endpoint n Control Register
Device n Endpoint n Address Register
Device n Endpoint n Count Register
Device n Endpoint n Status Register
Device n Endpoint n Count Result Register
Device n Port Select Register
Device n Interrupt Enable Register
Device n Address Register
Device n Status Register
Device n Frame Number Register
Device n SOF/EOP Count Register
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Device n Endpoint 0 Control Register [Device 1: 0x0200 Device 2: 0x0280]
Device n Endpoint 1 Control Register [Device 1: 0x0210 Device 2: 0x0290]
Device n Endpoint 2 Control Register [Device 1: 0x0220 Device 2: 0x02A0]
Device n Endpoint 3 Control Register [Device 1: 0x0230 Device 2: 0x02B0]
Device n Endpoint 4 Control Register [Device 1: 0x0240 Device 2: 0x02C0]
Device n Endpoint 5 Control Register [Device 1: 0x0250 Device 2: 0x02D0]
Device n Endpoint 6 Control Register [Device 1: 0x0260 Device 2: 0x02E0]
Device n Endpoint 7 Control Register [Device 1: 0x0270 Device 2: 0x02F0]
IN/OUT
Enable
Ignore
R/W
15
X
X
7
-
Sequence
Select
R/W
14
X
X
6
-
Enable
R/W
Stall
13
X
X
5
-
Enable
0x02n2
0xC08E/0xC0AE
Address (Device 1/Device 2)
0x02n0
0x02n4
0x02n6
0x02n8
0xC084/0xC0A4
0xC08C/0xC0AC
0xC090/0xCB0
0xC092/0xC0B2
0xC094/0xC0B4
R/W
ISO
12
X
X
4
-
Reserved
IN/OUT Ignore Enable (Bit 7)
The IN/OUT Ignore Enable bit forces endpoint 0 (EP0) to ignore
all IN and OUT requests. Set this bit so that EP0 only accepts
Setup packets at the start of each transfer. Clear this bit to accept
IN/OUT transactions. This bit only applies to EP0.
1: Ignore IN/OUT requests
0: Do not ignore IN/OUT requests
Interrupt
Enable
NAK
R/W
11
X
X
3
-
Direction
Select
R/W
10
X
X
2
-
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
W
R/W
X
X
9
1
-
CY7C67300
Enable
Page 38 of 99
R/W
Arm
X
X
8
0
-
Table
62.
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