CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet - Page 68

• Manufacturer Part Number: CY7C67300-100AXI
• Description: IC USB HOST/PERIPH CNTRL 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r
• Type: Host Programmable Embedded USBr

Specifications of CY7C67300-100AXI

• Package / Case: 100-LQFP
• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1865; CY7C67300-100AXI

Receive Bit Length (Bits [2:0])
The Receive Bit Length field controls whether a full byte or partial
byte is received. If Receive Bit Length is ‘000’ then a full byte is
received. If Receive Bit Length is ‘001’ to ‘111’, then the value
indicates the number of bits that are received.
SPI Interrupt Enable Register [0xC0CC] [R/W]
Table 108. SPI Interrupt Enable Register
Register Description
The SPI Interrupt Enable register controls the SPI port.
Receive Interrupt Enable (Bit 2)
The Receive Interrupt Enable bit enables or disables the byte
mode receive interrupt (RxIntVal).
1: Enable byte mode receive interrupt
0: Disable byte mode receive interrupt
Transmit Interrupt Enable (Bit 1)
The Transmit Interrupt Enable bit enables or disables the byte
mode transmit interrupt (TxIntVal).
SPI Status Register [0xC0CE] [R]
Table 109. SPI Status Register
Register Description
The SPI Status register is a read only register that provides
status for the SPI port.
FIFO Error Flag (Bit 7)
The FIFO Error Flag bit is a read only bit that indicates if a FIFO
error occurred. When this bit is set to ‘1’ and the Transmit Empty
Document #: 38-08015 Rev. *J
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
FIFO Error
Flag
15
15
R
0
7
0
0
7
0
-
-
-
14
14
0
6
0
0
6
0
-
-
-
-
...Reserved
13
13
0
5
0
0
5
0
-
-
-
-
Reserved
12
12
0
4
0
0
4
0
-
-
-
-
Reserved...
Reserved
1: Enables byte mode transmit interrupt
0: Disables byte mode transmit interrupt
Transfer Interrupt Enable (Bit 0)
The Transfer Interrupt Enable bit enables or disables the block
mode interrupt (XfrBlkIntVal).
1: Enables block mode interrupt
0: Disables block mode interrupt
Reserved
Write all reserved bits with ’0’.
bit of the SPI Control register is set to ‘1’, then a Tx FIFO
underflow occurred. Similarly, when set with the Receive Full bit
of the SPI Control register, an Rx FIFO overflow occured.This bit
automatically clears when the SPI FIFO Init Enable bit of the SPI
Control register is set.
1: Indicates FIFO error
0: Indicates no FIFO error
11
11
0
3
0
0
3
0
-
-
-
-
Interrupt
Receive
Interrupt
Receive
Enable
R/W
Flag
10
10
R
0
2
0
0
2
0
-
-
Transmit
Transmit
Interrupt
Interrupt
Enable
R/W
Flag
R
9
0
1
0
9
0
1
0
-
-
CY7C67300
Interrupt
Transfer
Interrupt
Transfer
Enable
Page 68 of 99
Flag
R/W
R
8
0
0
0
8
0
0
0
-
-
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