CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet - Page 9

• Manufacturer Part Number: CY7C67300-100AXI
• Description: IC USB HOST/PERIPH CNTRL 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r
• Type: Host Programmable Embedded USBr

Specifications of CY7C67300-100AXI

• Package / Case: 100-LQFP
• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1865; CY7C67300-100AXI

Host Port Interface
EZ-Host has an HPI interface. The HPI interface provides DMA
access to the EZ-Host internal memory by an external host, plus
a bidirectional mailbox register for supporting high level commu-
nication protocols. This port is designed to be the primary
high-speed connection to a host processor. Complete control of
EZ-Host can be accomplished through this interface via an
extensible API and communication protocol. Other than the
hardware communication protocols, a host processor has
identical control over EZ-Host whether connecting to the HPI or
HSS port. The HPI interface is exposed through GPIO pins.
HPI Features
■
■
■
■
■
■
■
■
■
HPI Pins
Table 12. HPI Interface Pins
Document #: 38-08015 Rev. *J
Notes
3. HPI_INT is for the Outgoing Mailbox interrupt.
4. HPI strobes are negative logic sampled on rising edge.
16-bit data bus interface
16 MB/s throughput
Auto-increment of address pointer for fast block mode transfers
Direct memory access (DMA) to internal memory
Bidirectional Mailbox register
Byte swapping
Complete access to internal memory
Complete control of SIEs through HPI
Dedicated HPI status register
Pin Name
nWR
nRD
nCS
D15
D14
D13
D12
INT
A1
A0
[3, 4]
Pin Number
46
47
48
49
50
52
56
57
58
59
Table 12. HPI Interface Pins (continued)
The two HPI address pins are used to address one of four
possible HPI port registers as shown in
Table 13. HPI Addressing
IDE Interface
EZ-Host has an IDE interface. The IDE interface supports PIO
mode 0-4 as specified in the Information Technology-AT
Attachment–4 with Packet Interface Extension (ATA/ATAPI-4)
Specification, T13/1153D Rev 18. There is no need for firmware
to use programmable wait states. The CPU read/write cycle is
automatically extended as needed for direct CPU to IDE
read/write accesses.
The EZ-Host IDE interface also has a BLOCK transfer mode that
allows EZ-Host to read/write large blocks of data to/from the IDE
data register and move it to/from the EZ-Host on-chip memory
directly without intervention of the CPU. The IDE interface is
exposed through GPIO pins.
achieved throughput for maximum block mode data transfer rate
(with IDE_IORDY true) for the various IDE PIO modes.
HPI Address
HPI Mailbox
HPI A[1:0]
HPI Status
HPI Data
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A1
0
0
1
1
Table 14 on page 10
60
61
65
66
86
87
89
90
91
92
93
94
Table
[3, 4]
CY7C67300
A0
0
1
0
1
13.
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