CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet - Page 50

• Manufacturer Part Number: CY7C67300-100AXI
• Description: IC USB HOST/PERIPH CNTRL 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r
• Type: Host Programmable Embedded USBr

Specifications of CY7C67300-100AXI

• Package / Case: 100-LQFP
• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1865; CY7C67300-100AXI

GPIO Control Register [0xC006] [R/W]
Table 77. GPIO Control Register
Register Description
The GPIO Control register configures the GPIO pins for various
interface options. It also controls the polarity of the GPIO
interrupt on IRQ1 (GPIO25) and IRQ0 (GPIO24).
Write Protect Enable (Bit 15)
The Write Protect Enable bit enables or disables the GPIO write
protect. When Write Protect is enabled, the GPIO Mode Select
[15:8] field is read only until a chip reset.
1: Enable Write Protect
0: Disable Write Protect
UD (Bit 14)
The UD bit routes the Host/Device 1A Port’s transmitter enable
status to GPIO[30]. This is for use with an external ESD
protection circuit when needed.
1: Route the signal to GPIO[30]
0 : Do not route the signal to GPIO[30]
SAS Enable (Bit 11)
The SAS Enable bit, when in SPI mode, reroutes the SPI port
SPI_nSSI pin to GPIO[15] rather then GPIO[9] or XD[9] (per
SG/SX).
1: Reroute SPI_nss to GPIO[30]
0: Leave SPI_nss on GPIO[9]
Mode Select (Bits [10:8])
The Mode Select field selects how GPIO[15:0] and GPIO[24:19]
are used as defined in
Table 78. Mode Select Definition
Document #: 38-08015 Rev. *J
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Mode Select
[10:8]
110
101
100
011
010
001
000
111
Write Protect
Reserved
SCAN — (HW) Scan diagnostic. For produc-
tion test only. Not for normal operation
HPI — Host Port Interface
IDE — Integrated Drive Electronics or
Reserved
Reserved
Reserved
GPIO — General Purpose Input Output
Enable
Enable
R/W
HSS
R/W
15
0
7
0
Table
GPIO Configuration
78.
HSS XD
Enable
R/W
R/W
UD
14
0
6
0
Enable
R/W
SPI
13
0
5
0
-
Reserved
SPI XD
Enable
R/W
12
0
4
0
-
HSS Enable (Bit 7)
The HSS Enable bit routes HSS to GPIO[26, 18:16]. If the HSS
XD Enable bit is set, it overrides this bit and HSS is routed to
XD[15:12].
1: HSS is routed to GPIO
0: HSS is not routed to GPIOs. GPIO[26, 18:16] are free for other
purposes
HSS XD Enable (Bit 6)
The HSS XD Enable bit routes HSS to XD[15:12] (external
memory data bus). This bit overrides the HSS Enable bit.
1: HSS is routed to XD[15:12]
0: HSS is not routed to XD[15:12]
SPI Enable (Bit 5)
The SPI Enable bit routes SPI to GPIO[11:8]. If the SAS Enable
bit is set, it overrides the SPI Enable and routes SPI_nSSI to
GPIO15. If the SPI XD Enable bit is set, it overrides both bits and
the SPI is routed to XD[11:8] (external memory data bus).
1: SPI is routed to GPIO[11:8]
0: SPI is not routed to GPIO[11:8]. GPIO[11:8] are free for other
purposes
SPI XD Enable (Bit 4)
The SPI XD Enable bit routes SPI to XD[11:8] (external memory
data bus). This bit overrides the SPI Enable bit.
1: SPI is routed to XD[11:8]
0: SPI is not routed to XD[11:8]
Interrupt 1 Polarity Select (Bit 3)
The Interrupt 1 Polarity Select bit selects the polarity for IRQ1.
1: Sets IRQ1 to rising edge
0: Sets IRQ1 to falling edge
Interrupt 1 Enable (Bit 2)
The Interrupt 1 Enable bit enables or disables IRQ1. The GPIO
bit on the interrupt Enable register must also be set in order for
this for this interrupt to be enabled.
1: Enable IRQ1
0: Disable IRQ1
Polarity Select
Interrupt 1
Enable
SAS
R/W
R/W
11
0
3
0
Interrupt 1
Enable
R/W
R/W
10
0
2
0
Polarity Select
Interrupt 0
Select
Mode
R/W
R/W
9
0
1
0
CY7C67300
Interrupt 0
Enable
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R/W
R/W
8
0
0
0
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