CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet - Page 35

• Manufacturer Part Number: CY7C67300-100AXI
• Description: IC USB HOST/PERIPH CNTRL 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r
• Type: Host Programmable Embedded USBr

Specifications of CY7C67300-100AXI

• Package / Case: 100-LQFP
• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1865; CY7C67300-100AXI

SOF/EOP Interrupt Enable (Bit 9)
The SOF/EOP Interrupt Enable bit enables or disables the
SOF/EOP timer interrupt
1: Enable SOF/EOP timer interrupt
0: Disable SOF/EOP timer interrupt
Port B Wake Interrupt Enable (Bit 7)
The Port B Wake Interrupt Enable bit enables or disables the
remote wakeup interrupt for Port B
1: Enable remote wakeup interrupt for Port B
0: Disable remote wakeup interrupt for Port B
Port A Wake Interrupt Enable (Bit 6)
The Port A Wake Interrupt Enable bit enables or disables the
remote wakeup interrupt for Port A
1: Enable remote wakeup interrupt for Port A
0: Disable remote wakeup interrupt for Port A
Port B Connect Change Interrupt Enable (Bit 5)
The Port B Connect Change Interrupt Enable bit enables or
disables the Port B Connect Change interrupt on Port B. This
interrupt triggers when either a device is inserted (SE0 state to J
state) or a device is removed (J state to SE0 state).
Host n Status Register [R/W]
■
■
Table 58. Host n Status Register
Register Description
The Host n Status register provides status information for host
operation. Pending interrupts can be cleared by writing a ‘1’ to
the corresponding bit. This register can be accessed by the HPI
interface.
VBUS Interrupt Fla g (Bit 15)
The VBUS Interrupt Flag bit indicates the status of the OTG
VBUS interrupt (only for Port 1A). When enabled this interrupt
triggers on both the rising and falling edge of VBUS at 4.4V. This
bit is only available for Host 1 and is a reserved bit in Host 2.
Document #: 38-08015 Rev. *J
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Host 1 Status Register 0xC090
Host 2 Status Register 0xC0B0
Wake Interrupt
VBUS Interrupt
Port B
Flag
R/W
7
X
Flag
R/W
15
X
Wake Interrupt
Port A
Flag
R/W
ID Interrupt
6
X
Flag
R/W
14
X
Port B Connect
Interrupt Flag
Change
R/W
X
5
13
X
-
Change Interrupt
Port A Connect
12
X
Flag
R/W
-
4
X
1: Enable Connect Change interrupt
0: Disable Connect Change interrupt
Port A Connect Change Interrupt Enable (Bit 4)
The Port A Connect Change Interrupt Enable bit enables or
disables the Connect Change interrupt on Port A. This interrupt
triggers when either a device is inserted (SE0 state to J state) or
a device is removed (J state to SE0 state).
1: Enable Connect Change interrupt
0: Disable Connect Change interrupt
Done Interrupt Enable (Bit 0)
The Done Interrupt Enable bit enables or disables the USB
Transfer Done interrupt. The USB Transfer Done triggers when
either the host responds with an ACK, or a device responds with
any of the following: ACK, NAK, STALL, or Timeout. This
interrupt is used for both Port A and Port B.
1: Enable USB Transfer Done interrupt
0: Disable USB Transfer Done interrupt
Reserved
Write all reserved bits with ’0’.
1: Interrupt triggered
0: Interrupt did not trigger
ID Interrupt Flag (Bit 14)
The ID Interrupt Flag bit indicates the status of the OTG ID
interrupt (only for Port 1A). When enabled this interrupt triggers
on both the rising and falling edge of the OTG ID pin. This bit is
only available for Host 1 and is a reserved bit in Host 2.
1: Interrupt triggered
0: Interrupt did not trigger
Reserved
11
X
-
Port B
Status
SE0
R/W
X
3
10
X
-
Port A
Status
SE0
R/W
2
X
Interrupt Flag
SOF/EOP
Reserved
R/W
X
9
X
1
-
CY7C67300
Done Interrupt
Reserved
Flag
R/W
Page 35 of 99
X
0
X
8
-
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