CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet - Page 48

• Manufacturer Part Number: CY7C67300-100AXI
• Description: IC USB HOST/PERIPH CNTRL 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r
• Type: Host Programmable Embedded USBr

Specifications of CY7C67300-100AXI

• Package / Case: 100-LQFP
• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1865; CY7C67300-100AXI

Device n SOF/EOP Count Register [W]
■
■
Table 73. Device n SOF/EOP Count Register
Register Description
The Device n SOF/EOP Count register is written with the time
expected between receiving a SOF/EOP. If the SOF/EOP
counter expires before an SOF/EOP is received, an SOF/EOP
Timeout Interrupt can be generated. The SOF/EOP Timeout
Interrupt Enable and SOF/EOP Timeout Interrupt Flag are
located in the Device n Interrupt Enable and Status registers
respectively.
Set the SOF/EOP count slightly greater than the expected
SOF/EOP interval. The SOF/EOP counter decrements at a
12 MHz rate. Therefore, in the case of an expected 1 ms
SOF/EOP interval, the SOF/EOP count is set slightly greater
than 0x2EE0.
Count (Bits [13:0])
The Count field contains the current value of the SOF/EOP down
counter. At power up and reset, this value is set to 0x2EE0 and
for expected 1 ms SOF/EOP intervals, this SOF/EOP count is
increased slightly.
OTG Control Register [0xC098] [R/W]
Table 75. OTG Control Register
Register Description
The OTG Control register allows control and monitoring over the
OTG port on Port1A. Note that the D± pull up and pull down bits
override the setting in the USB 0 Control register for this port.
Document #: 38-08015 Rev. *J
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Device 1 SOF/EOP Count Register 0xC094
Device 2 SOF/EOP Count Register 0xC0B4
Pull-down Enable
15
0
-
Reserved
15
R
0
7
1
-
R/W
D+
7
0
Reserved
14
0
-
14
R
0
6
1
-
Pull-down Enable
Pull-up Enable
VBUS
R/W
R/W
13
D–
0
6
0
13
R
R
1
5
1
Receive
Disable
R/W
5
0
-
12
0
12
R
R
0
4
0
Reserved
...Count
Charge Pump
Reserved
Write all reserved bits with ’0’.
OTG Control Registers
There is one register dedicated for On-The-Go operation. This
register is covered in this section and summarized in
Table 74. OTG Register
VBUS Pull-up Enable (Bit 13)
The VBUS Pull-up Enable bit enables or disables a 500 ohm pull
up resistor onto OTG VBus.
1: 500 ohm pull up resistor enabled
0: 500 ohm pull up resistor disabled
OTG Control Register
4
0
-
Enable
R/W
11
0
Register Name
11
R
R
3
0
1
3
0
-
Discharge Enable
Count...
VBUS
R/W
10
0
OTG Data
Status
10
R
2
0
R
1
R
X
2
Pull-up Enable
Address
C098H
R/W
D+
9
0
R
1
0
R
9
1
Status
ID
R
X
1
CY7C67300
Pull-up Enable
Page 48 of 99
VBUS Valid
R
0
0
R
8
0
R/W
D–
Flag
Table
8
0
R/W
R/W
R
X
0
74.
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