Z84C9008VSG Zilog, Z84C9008VSG Datasheet - Page 100

• Manufacturer Part Number: Z84C9008VSG
• Description: IC 8MHZ Z80 KIO 84-PLCC
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z84C9008VSG

• Processor Type: Z80
• Features: Serial/Parallel Input/Output, Counter/Timer Circuit
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 84-LCC (J-Lead)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Cpu Speed: 8MHz
• Digital Ic Case Style: LCC
• No. Of Pins: 84
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Rohs Compliant: Yes
• Base Number: 84
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

80
UM008005-0205
Z80 CPU
User’s Manual
Z80 Instruction Description
When inputting or outputting a byte between a memory location and an I/O
device (
Register is
from I/O devices using
Sign Flag
The Sign Flag (S) stores the state of the most-significant bit of the
Accumulator (bit 7). When the Z80 performs arithmetic operations on
signed numbers, the binary twos-complement notation is used to represent
and process numeric information. A positive number is identified by a
Bit 7. A negative number is identified by a 1. The binary equivalent of the
magnitude of a positive number is stored in bits 0 to 6 for a total range of
from
of the equivalent positive number. The total range for negative numbers is
from –
When inputting a byte from an I/O device to a register using an IN r, (C)
instruction, the S Flag indicates either positive (S = 0) or negative (S = 1)
data.
Execution time (E.T.) for each instruction is given in microseconds for an
assumed 4 MHz clock. Total machine cycles (M) are indicated with total
clock periods (T States). Also indicated are the number of T States for each
M cycle. For example:
M Cycles: 2T States: 7(4,3) 4 MHzE.T.: 1.75
indicates that the instruction consists of 2 machine cycles. The first cycle
contains 4 clock periods (T States). The second cycle contains 3 clock
periods for a total of 7 clock periods or T States. The instruction executes in
1.75 microseconds.
Register format is indicated for each instruction with the most-significant
bit to the left and the least-significant bit to the right.
0
1
to
INI
to –
127
0
,
, the Z flag is
128
IND
. A negative number is represented by the twos complement
.
,
OUTI
IN r
, and
1
, otherwise the Z flag is
, (
OUTD
C
), the Z flag is set to indicate a 0-byte input.
), if the result of decrementing the
0
. Also for byte inputs
Z80 Instruction Set
B
0
in