Z84C9008VSG Zilog, Z84C9008VSG Datasheet - Page 32

• Manufacturer Part Number: Z84C9008VSG
• Description: IC 8MHZ Z80 KIO 84-PLCC
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z84C9008VSG

• Processor Type: Z80
• Features: Serial/Parallel Input/Output, Counter/Timer Circuit
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 84-LCC (J-Lead)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Cpu Speed: 8MHz
• Digital Ic Case Style: LCC
• No. Of Pins: 84
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Rohs Compliant: Yes
• Base Number: 84
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12
UM008005-0205
Z80 CPU
User’s Manual
CLK
Instruction Fetch
T Cycle
T1
Figure 4.
Figure 5 depicts the timing during an M1 (opcode fetch) cycle. The PC is
placed on the address bus at the beginning of the M1 cycle. One half clock
cycle later the MREQ signal goes active. At this time the address to the
memory has had time to stabilize so that the falling edge of MREQ can be
used directly as a chip enable clock to dynamic memories. The RD line also
goes active to indicate that the memory read data should be enabled onto the
CPU data bus. The CPU samples the data from the memory on the data bus
with the rising edge of the clock of state T3 and this same edge is used by
the CPU to turn off the RD and MREQ signals. Thus, the data has already
been sampled by the CPU before the RD signal becomes inactive. Clock
state T3 and T4 of a fetch cycle are used to refresh dynamic memories. The
CPU uses this time to decode and execute the fetched instruction so that no
other operation could be performed at this time.
During T3 and T4, the lower seven bits of the address bus contain a memory
refresh address and the RFSH signal becomes active tindicating that a
refresh read of all dynamic memories must be accomplished. An RD signal
is not generated during refresh time to prevent data from different memory
Machine Cycle
(Opcode Fetch)
T2
M1
Basic CPU Timing Example
T3
Instruction Cycle
T1
(Memory Read)
M2
T2
T3
T1
(Memory Write)
M3
T2
T3
Overview