Z84C9008VSG Zilog, Z84C9008VSG Datasheet - Page 35

• Manufacturer Part Number: Z84C9008VSG
• Description: IC 8MHZ Z80 KIO 84-PLCC
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z84C9008VSG

• Processor Type: Z80
• Features: Serial/Parallel Input/Output, Counter/Timer Circuit
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 84-LCC (J-Lead)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Cpu Speed: 8MHz
• Digital Ic Case Style: LCC
• No. Of Pins: 84
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Rohs Compliant: Yes
• Base Number: 84
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008005-0205
Bus Request/Acknowledge Cycle
A
D
D
15
7
7
IORQ
— D
WAIT
— D
— A
CLK
Figure 7.
Figure 8 illustrates the timing for a Bus Request/Acknowledge cycle. The
BUSREQ signal is sampled by the CPU with the rising edge of the last clock
period of any machine cycle. If the BUSREQ signal is active, the CPU sets
its address, data, and tristate control signals to the high-impedance state with
the rising edge of the next clock pulse. At that time, any external device can
control the buses to transfer data between memory and I/O devices. (This
operation is generally known as Direct Memory Access [DMA] using cycle
stealing.) The maximum time for the CPU to respond to a bus request is the
length of a machine cycle and the external controller can maintain control of
the bus for as many clock cycles as is required. If very long DMA cycles are
used, and dynamic memories are used, the external controller also performs
the refresh function. This situation only occurs if very large blocks of data
WR
RD
0
0
0
*Automatically inserted WAIT state
Input or Output Cycles
T
1
Port Address
T
2
Out
TW*
In
T
3
User’s Manual
T
Z80 CPU
1
Overview
Write
Cycle
Read
Cycle
15