Z84C9008VSG Zilog, Z84C9008VSG Datasheet - Page 297

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Z84C9008VSG

Manufacturer Part Number
Z84C9008VSG
Description
IC 8MHZ Z80 KIO 84-PLCC
Manufacturer
Zilog
Series
Z80r
Datasheets

Specifications of Z84C9008VSG

Processor Type
Z80
Features
Serial/Parallel Input/Output, Counter/Timer Circuit
Speed
8MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
84-LCC (J-Lead)
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Cpu Speed
8MHz
Digital Ic Case Style
LCC
No. Of Pins
84
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Rohs Compliant
Yes
Base Number
84
Clock Frequency
8MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z84C9008VSG
Manufacturer:
Zilog
Quantity:
13
Part Number:
Z84C9008VSG
Manufacturer:
ZILOG
Quantity:
6 221
Part Number:
Z84C9008VSG
Manufacturer:
Zilog
Quantity:
10 000
Operation:
Op Code:
Description: The contents of register C are placed on the bottom half (A0 through A7)
Condition Bits Affected:
UM008005-0205
(HL) ← (C), B ← 131, HL ← HL1
INDR
of the address bus to select the I/O device at one of 256 possible ports.
Register B is used as a byte counter, and its contents are placed on the top
half (A8 through A15) of the address bus at this time. Then one byte from
the selected port is placed on the data bus and written to the CPU. The
contents of the HL register pair are placed on the address bus and the
input byte is written to the corresponding location of memory. Then HL
and the byte counter are decremented. If decrementing causes B to go to
zero, the instruction is terminated. If B is not zero, the PC is decremented
by two and the instruction repeated. Interrupts are recognized and two
refresh cycles are executed after each data transfer.
When B is set to zero prior to instruction execution, 256 bytes of data are
input.
If B ≠ 0
If B = 0:
S is unknown
Z is set
H is unknown
P/V is unknown
N is set
1
1
1
0
M Cycles
5
M Cycles
4
1
1
0
1
1
1
T States
21 (4, 5, 3, 4, 5)
T States
16 (4, 5, 3, 4)
INDR
1
0
0
1
1
0
ED
BA
4 MHz E.T.
4 MHz E.T.
5.25
4.00
Z80 Instruction Set
User’s Manual
Z80 CPU
277

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