Z84C9008VSG Zilog, Z84C9008VSG Datasheet - Page 303
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Z84C9008VSG
Manufacturer Part Number
Z84C9008VSG
Description
IC 8MHZ Z80 KIO 84-PLCC
Manufacturer
Zilog
Series
Z80r
Specifications of Z84C9008VSG
Processor Type
Z80
Features
Serial/Parallel Input/Output, Counter/Timer Circuit
Speed
8MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
84-LCC (J-Lead)
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Cpu Speed
8MHz
Digital Ic Case Style
LCC
No. Of Pins
84
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Rohs Compliant
Yes
Base Number
84
Clock Frequency
8MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z84C9008VSG
Manufacturer:
Zilog
Quantity:
13
Company:
Part Number:
Z84C9008VSG
Manufacturer:
ZILOG
Quantity:
6 221
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Operation:
Op Code:
Description: The contents of the HL register pair are placed on the address bus to select
Condition Bits Affected:
UM008005-0205
(C) ← (HL), B ← B -1, HL ← HL + 1
OTIR
a location in memory. The byte contained in this memory location is tempo-
rarily stored in the CPU. Then, after the byte counter (B) is decremented, the
contents of register C are placed on the bottom half (A0 through A7) of the
address bus to select the I/O device at one of 256 possible ports. Register B
may be used as a byte counter, and its decremented value is placed on the top
half (A8 through A15) of the address bus at this time. Next, the byte to be
output is placed on the data bus and written to the selected peripheral device.
Then register pair HL is incremented. If the decremented B register is not
zero, the Program Counter (PC) is decremented by two and the instruction is
repeated. If B has gone to zero, the instruction is terminated. Interrupts are
recognized and two refresh cycles are executed after each data transfer.
If B ≠ 0:
If B = 0:
1
1
1
0
Note: When B is set to zero prior to instruction execution, the instruc-
tion outputs 256 bytes of data.
M Cycles
M Cycles
1
1
5
4
0
1
1
0
21 (4, 5, 3, 4, 5)
OTIR
16 (4, 5, 3, 4)
1
0
T States
T States
0
1
1
1
ED
B3
4 MHz E.T.
4 MHz E.T.
5.25
4.00
Z80 Instruction Set
User’s Manual
Z80 CPU
283
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