Z84C9008VSG Zilog, Z84C9008VSG Datasheet - Page 34

• Manufacturer Part Number: Z84C9008VSG
• Description: IC 8MHZ Z80 KIO 84-PLCC
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z84C9008VSG

• Processor Type: Z80
• Features: Serial/Parallel Input/Output, Counter/Timer Circuit
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 84-LCC (J-Lead)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Cpu Speed: 8MHz
• Digital Ic Case Style: LCC
• No. Of Pins: 84
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Rohs Compliant: Yes
• Base Number: 84
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14
UM008005-0205
Z80 CPU
User’s Manual
Input or Output Cycles
A
D
15
7
MREQ
— D
WAIT
— A
CLK
WR
RD
it can be used directly as a R/W pulse to virtually any type of semiconductor
memory. Furthermore, the WR signal goes inactive one-half T state before
the address and data bus contents are changed so that the overlap
requirements for almost any type of semiconductor memory type is met.
Figure 6.
Figure 7 illustrates an I/O read or I/O write operation. During I/O operations
a single wait state is automatically inserted. The reason is that during I/O
operations, the time from when the IORQ signal goes active until the CPU
must sample the WAIT line is very short. Without this extra state, sufficient
time does not exist for an I/O port to decode its address and activate the
WAIT line if a wait is required. Also, without this wait state, it is difficult to
design MOS I/O devices that can operate at full CPU speed. During this wait
state time, the WAIT request signal is sampled.
During a read I/O operation, the RD line is used to enable the addressed port
onto the data bus just as in the case of a memory read. For I/O write
operations, the WR line is used as a clock to the I/O port.
0
0
Memory Address
Memory Read or Write Cycle
Memory Read Cycle
T
2
In
T
3
T
1
Memory Address
Memory Write Cycle
T
Data Out
2
T
3
Overview