Z84C9008VSG Zilog, Z84C9008VSG Datasheet - Page 38
![no-image](/images/manufacturer_photos/0/7/729/zilog_sml.jpg)
Z84C9008VSG
Manufacturer Part Number
Z84C9008VSG
Description
IC 8MHZ Z80 KIO 84-PLCC
Manufacturer
Zilog
Series
Z80r
Specifications of Z84C9008VSG
Processor Type
Z80
Features
Serial/Parallel Input/Output, Counter/Timer Circuit
Speed
8MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
84-LCC (J-Lead)
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Cpu Speed
8MHz
Digital Ic Case Style
LCC
No. Of Pins
84
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Rohs Compliant
Yes
Base Number
84
Clock Frequency
8MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z84C9008VSG
Manufacturer:
Zilog
Quantity:
13
Company:
Part Number:
Z84C9008VSG
Manufacturer:
ZILOG
Quantity:
6 221
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18
UM008005-0205
Z80 CPU
User’s Manual
HALT Exit
A
15
MREQ
RFSH
— A
CLK
NMI
RD
Figure 10. Non-Maskable Interrupt Request Operation
Whenever a software HALT instruction is executed, the CPU executes
NOPs until an interrupt is received (either a non-maskable or a maskable
interrupt while the interrupt flip-flop is enabled). The two interrupt lines are
sampled with the rising clock edge during each T4 state as depicted in
Figure 11. If a non-maskable interrupt has been received or a maskable
interrupt has been received and the interrupt enable flip-flop is set, then the
HALT state is exited on the next rising clock edge. The following cycle is an
interrupt acknowledge cycle corresponding to the type of interrupt that was
received. If both are received at this time, then the non-maskable one is
acknowledged since it has highest priority. The purpose of executing NOP
instructions while in the HALT state is to keep the memory refresh signals
active. Each cycle in the HALT state is a normal M1 (fetch) cycle except
that the data received from the memory is ignored and a NOP instruction is
forced internally to the CPU. The HALT acknowledge signal is active
during this time indicating that the processor is in the HALT state.
M1
0
Last M Cycle
Last T State
T
1
PC
T
2
M1
T
3
Refresh
T
4
Overview
T
1
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