Z84C9008VSG Zilog, Z84C9008VSG Datasheet - Page 33

• Manufacturer Part Number: Z84C9008VSG
• Description: IC 8MHZ Z80 KIO 84-PLCC
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z84C9008VSG

• Processor Type: Z80
• Features: Serial/Parallel Input/Output, Counter/Timer Circuit
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 84-LCC (J-Lead)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Cpu Speed: 8MHz
• Digital Ic Case Style: LCC
• No. Of Pins: 84
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Rohs Compliant: Yes
• Base Number: 84
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008005-0205
A
D
15
7
MREQ
RFSH
WAIT
— D
— A
CLK
RD
M1
Memory Read Or Write
0
0
segments from being gated onto the data bus. The MREQ signal during
refresh time should be used to perform a refresh read of all memory
elements. The refresh signal can not be used by itself because the refresh
address is only guaranteed to be stable during MREQ time.
Figure 5.
Figure 6 illustrates the timing of memory read or write cycles other than an
Op Code fetch cycle. These cycles are generally three clock periods long
unless wait states are requested by the memory through the WAIT signal.
The MREQ signal and the RD signal are used the same as in the fetch cycle.
In a memory write cycle, the MREQ also becomes active when the address
bus is stable so that it can be used directly as a chip enable for dynamic
memories. The WR line is active when data on the data bus is stable so that
T
PC
1
Instruction Op Code Fetch
T
2
M1 Cycle
IN
T
3
Refresh Address
T
4
T
User’s Manual
1
Z80 CPU
Overview
13