Z84C9008VSG Zilog, Z84C9008VSG Datasheet - Page 36

• Manufacturer Part Number: Z84C9008VSG
• Description: IC 8MHZ Z80 KIO 84-PLCC
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z84C9008VSG

• Processor Type: Z80
• Features: Serial/Parallel Input/Output, Counter/Timer Circuit
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 84-LCC (J-Lead)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Cpu Speed: 8MHz
• Digital Ic Case Style: LCC
• No. Of Pins: 84
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Rohs Compliant: Yes
• Base Number: 84
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16
UM008005-0205
Z80 CPU
User’s Manual
MREQ, RD
WR. IORQ,
A
BUSREQ
Interrupt Request/Acknowledge Cycle
BUSACK
D
15
7
RFSH
— D
— A
CLK
0
0
are transferred under DMA control. During a bus request cycle, the CPU
cannot be interrupted by either an NMI or an INT signal.
Figure 8.
Figure 9 illustrates the timing associated with an interrupt cycle. The CPU
samples the interrupt signal (INT) with the rising edge of the last clock at the
end of any instruction. The signal is not accepted if the internal CPU
software controlled interrupt enable flip-flop is not set or if the BUSREQ
signal is active. When the signal is accepted, a special M1 cycle is
generated. During this special M1 cycle, the IORQ signal becomes active
(instead of the normal MREQ) to indicate that the interrupting device can
place an 8-bit vector on the data bus. Two wait states are automatically
added to this cycle. These states are added so that a ripple priority interrupt
scheme can be easily implemented. The two wait states allow sufficient time
for the ripple signals to stabilize and identify which
I/O device must insert the response vector. Refer to Chapter 6 for details on
how the interrupt response vector is utilized by the CPU.
Bus Request/Acknowledge Cycle
Sample
Any M Cycle
Last T State
T
X
Bus Available Status
Sample
Floating
T
X
T
X
Overview
T
1