Z84C9008VSG Zilog, Z84C9008VSG Datasheet - Page 89
Z84C9008VSG
Manufacturer Part Number
Z84C9008VSG
Description
IC 8MHZ Z80 KIO 84-PLCC
Manufacturer
Zilog
Series
Z80r
Specifications of Z84C9008VSG
Processor Type
Z80
Features
Serial/Parallel Input/Output, Counter/Timer Circuit
Speed
8MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
84-LCC (J-Lead)
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Cpu Speed
8MHz
Digital Ic Case Style
LCC
No. Of Pins
84
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Rohs Compliant
Yes
Base Number
84
Clock Frequency
8MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z84C9008VSG
Manufacturer:
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Quantity:
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Company:
Part Number:
Z84C9008VSG
Manufacturer:
ZILOG
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UM008005-0205
Address
N, N+1
N+2 to N+9
N+10,N+11
N + 12
JUMP JP
JUMP JR
JUMP JP
CALL
Decrement B, Jump
If Non Zero DJNZ
Return RE
Return From
INT RETI
Return From
Non Maskable
INT RETN
Table 16. Jump, Call, and Return Group
The instruction
byte, relative jump instruction decrements the B register and the jump
occurs if the B register has not been decremented to zero. The relative
displacement is expressed as a signed two’s complement number. A
simple example of its use is:
IMMED.
EXT.
RELATIVE
Register
INDIR.
IMMED.
EXT.
RELATIVE
REGISTER
INDIR.
Instruction
LD B, 7
(Perform a sequence of instructions)
DJNZ -8
(Next Instruction)
DJNZ
nn
PC+e
(HL)
(IX)
(IY)
nn
PC+e
(SP)
(SP+1)
is used to facilitate program loop control. This two
Condition
Un-
Cond.
C3
n
n
18
e-2
EB
DD
E9
FD
E9
CD
n
n
C9
ED
4D
ED
45
Carry Non
D8
n
n
38
e-2
DC
n
n
D8
Carry
D2
n
n
30
e-2
D4
n
n
D0
Zero
CA
n
n
28
e-2
CC
n
n
C8
Z80 CPU Instruction Description
Comments
: set B register to count of 7
: loop to be performed 7 times
: to jump from N+12 to N+2
Non
Zero
C2
n
n
20
e-2
C4
n
n
C0
Parity
Even
EA
n
n
EC
n
n
E8
Parity
Odd
E2
n
n
E4
n
n
E0
User’s Manual
Sign
Neg
FA
n
n
FC
n
n
F8
Z80 CPU
Sign
Pos
F2
n
n
F4
n
n
F0
Reg
B≠0
10
e-2
69
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