KSZ8842-16MQL Micrel Inc, KSZ8842-16MQL Datasheet - Page 124

• Manufacturer Part Number: KSZ8842-16MQL
• Description: IC SWITCH 10/100 16BIT 128PQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8842-16MQL

• Data Rate: 100Mbps
• Controller Type: Ethernet Switch Controller
• Interface: PCI
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3u
• Supply Current: 122mA
• Supply Voltage Range: 3.1V To 3.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: QFP
• No. Of: RoHS Compliant
• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.5V
• Operating Supply Voltage (min): 3.1V
• Operating Temperature Classification: Commercial
• Interface Type: PCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1634 - BOARD EVALUATION KSZ8842-16MQL
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-1478-5

Acronyms and Glossary
BIU
BPDU Bridge Protocol Data Unit
CMOS Complementary Metal Oxide Semiconductor
CRC Cyclic Redundancy Check
Cut-through switch
DA
DMA Direct Memory Access
EEPROM
EISA Extended Industry Standard Architecture
EMI
FCS Frame Check Sequence
FID
IGMP Internet Group Management Protocol
IPG
ISI
ISA
Jumbo Packet
MDI
Micrel Confidential
November 2005
Bus Interface Unit
Destination Address
Electro-Magnetic Interference
Frame or Filter ID
Inter-Packet Gap
Inter-Symbol Interference
Industry Standard Architecture
Medium Dependent Interface
Electronically Erasable Programmable Read-only Memory
The host interface function that performs code conversion, buffering,
A time delay between successive data packets mandated by the
and the like required for communications to and from a network.
A packet containing ports, addresses, etc. to make sure data being
passed through a bridged network arrives at its proper destination.
A common semiconductor manufacturing technique in which positive
and negative types of transistors are combined to form a current gate
that in turn forms an effective means of controlling electrical current
through a chip.
A common technique for detecting data transmission errors
Ethernet is 32 bits long.
A switch typically processes received packets by reading in the full
packet (storing), then processing the packet to determine where it
needs to go, then forwarding it. A cut-through switch simply reads in the
first bit of an incoming packet and forwards the packet. Cut-through
switches do not store the packet.
The address to send packets.
A design in which memory on a chip is controlled independently of the
CPU.
A design in which memory on a chip can be erased by exposing it to an
electrical charge.
A bus architecture designed for PCs using 80x86 processors, or an Intel
80386, 80486 or Pentium microprocessor. EISA buses are 32 bits wide
and support multiprocessing.
A naturally occurring phenomena when the electromagnetic field of one
device disrupts, impedes or degrades the electromagnetic field of
another device by coming into proximity with it. In computer technology,
computer devices are susceptible to EMI because electromagnetic
fields are a byproduct of passing electricity through a wire. Data lines
that have not been properly shielded are susceptible to data corruption
by EMI.
See CRC.
Specifies the frame identifier. Alternately is the filter identifier.
The protocol defined by RFC 1112 for IP multicast transmissions.
network standard for protocol reasons. In Ethernet, the medium has to
be "silent" (i.e., no data transfer) for a short period of time before a node
can consider the network idle and start to transmit. IPG is used to
correct timing differences between a transmitter and receiver. During
the IPG, no data is transferred, and information in the gap can be
discarded or additions inserted without impact on data integrity.
T
affecting or interfering with each other.
A bus architecture used in the IBM PC/XT and PC/AT.
A packet larger than the standard Ethernet packet (1500 bytes). Large
packet sizes allow for more efficient use of bandwidth, lower overhead,
less processing, etc.
An Ethernet port connection that allows network hubs or switches to
connect to other hubs or switches without a null-modem, or crossover,
he disruption of transmitted code caused by adjacent pulses
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KSZ8842-16/32 MQL/MVL
. CRC for
Rev. 1.4