KSZ8842-16MQL Micrel Inc, KSZ8842-16MQL Datasheet - Page 5

• Manufacturer Part Number: KSZ8842-16MQL
• Description: IC SWITCH 10/100 16BIT 128PQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8842-16MQL

• Data Rate: 100Mbps
• Controller Type: Ethernet Switch Controller
• Interface: PCI
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3u
• Supply Current: 122mA
• Supply Voltage Range: 3.1V To 3.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: QFP
• No. Of: RoHS Compliant
• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.5V
• Operating Supply Voltage (min): 3.1V
• Operating Temperature Classification: Commercial
• Interface Type: PCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1634 - BOARD EVALUATION KSZ8842-16MQL
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-1478-5

Bus Interface Unit (BIU)......................................................................................................... 30
Queue Management Unit (QMU) ........................................................................................... 35
Advanced Switch Functions ................................................................................................. 38
CPU Interface I/O Registers .................................................................................................. 45
Register Map: Switch & MAC/PHY........................................................................................ 54
Micrel Confidential
November 2005
Asynchronous Interface ....................................................................................................................................................32
Synchronous Interface ......................................................................................................................................................33
Summary ..........................................................................................................................................................................33
BIU Implementation Principles ..........................................................................................................................................34
Transmit Queue (TXQ) Frame Format..............................................................................................................................35
Receive Queue (RXQ) Frame Format ..............................................................................................................................36
Spanning Tree Support.....................................................................................................................................................38
IGMP Support ...................................................................................................................................................................39
IPv6 MLD Snooping ..........................................................................................................................................................39
Port Mirroring Support.......................................................................................................................................................39
IEEE 802.1Q VLAN Support .............................................................................................................................................40
QoS Priority Support .........................................................................................................................................................40
Port-Based Priority............................................................................................................................................................40
802.1p-Based Priority .......................................................................................................................................................40
DiffServ based Priority ......................................................................................................................................................41
Rate Limiting Support .......................................................................................................................................................41
MAC Filtering Function .....................................................................................................................................................42
Configuration Interface......................................................................................................................................................42
EEPROM Interface ...........................................................................................................................................................42
Loopback Support.............................................................................................................................................................43
I/O Registers .....................................................................................................................................................................45
Internal I/O Space Mapping ..............................................................................................................................................46
Bit Type Definition.............................................................................................................................................................54
Bank 0-63 Bank Select Register (0x0E): BSR (same location in all Banks)......................................................................54
Bank 0 Base Address Register (0x00): BAR.....................................................................................................................54
Bank 0 Bus Error Status Register (0x06): BESR ..............................................................................................................55
Bank 0 Bus Burst Length Register (0x08): BBLR .............................................................................................................55
Bank 1: Reserved .............................................................................................................................................................55
Bank 2 Host MAC Address Register Low (0x00): MARL ..................................................................................................55
Bank 2 Host MAC Address Register Middle (0x02): MARM .............................................................................................56
Bank 2 Host MAC Address Register High (0x04): MARH .................................................................................................56
Bank 3 On-Chip Bus Control Register (0x00): OBCR .......................................................................................................56
Bank 3 EEPROM Control Register (0x02): EEPCR ..........................................................................................................57
Bank 3 Memory BIST INFO Register (0x04): MBIR ..........................................................................................................57
Bank 3 Global Reset Register (0x06): GRR......................................................................................................................57
Bank 3 Bus Configuration Register (0x08): BCFG ............................................................................................................58
Banks 4—15: Reserved ....................................................................................................................................................58
Bank 16 Transmit Control Register (0x00): TXCR ............................................................................................................58
Bank 16 Transmit Status Register (0x02): TXSR..............................................................................................................58
Bank 16 Receive Control Register (0x04): RXCR.............................................................................................................59
Bank 16 TXQ Memory Information Register (0x08): TXMIR .............................................................................................59
Bank 16 RXQ Memory Information Register (0x0A): RXMIR............................................................................................60
Bank 17 TXQ Command Register (0x00): TXQCR ...........................................................................................................60
Bank 17 RXQ Command Register (0x02): RXQCR ..........................................................................................................60
Bank 17 TX Frame Data Pointer Register (0x04): TXFDPR .............................................................................................60
Bank 17 RX Frame Data Pointer Register (0x06): RXFDPR ............................................................................................61
Bank 17 QMU Data Register Low (0x08): QDRL ..............................................................................................................61
Bank 17 QMU Data Register High (0x0A): QDRH ............................................................................................................61
Bank 18 Interrupt Enable Register (0x00): IER.................................................................................................................62
Bank 18 Interrupt Status Register (0x02): ISR..................................................................................................................63
Bank 18 Receive Status Register (0x04): RXSR ..............................................................................................................64
“IGMP” Snooping............................................................................................................................................................39
“Multicast Address Insertion” in the Static MAC Table....................................................................................................39
Far-end Loopback ..........................................................................................................................................................43
Near-end (Remote) Loopback ........................................................................................................................................43
5
KSZ8842-16/32 MQL/MVL
Rev. 1.4