KSZ8842-16MQL Micrel Inc, KSZ8842-16MQL Datasheet - Page 59

• Manufacturer Part Number: KSZ8842-16MQL
• Description: IC SWITCH 10/100 16BIT 128PQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8842-16MQL

• Data Rate: 100Mbps
• Controller Type: Ethernet Switch Controller
• Interface: PCI
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3u
• Supply Current: 122mA
• Supply Voltage Range: 3.1V To 3.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: QFP
• No. Of: RoHS Compliant
• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.5V
• Operating Supply Voltage (min): 3.1V
• Operating Temperature Classification: Commercial
• Interface Type: PCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1634 - BOARD EVALUATION KSZ8842-16MQL
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-1478-5

Bank 16 Receive Control Register (0x04): RXCR
This register holds control information programmed by the CPU to control the receive function.
Bank 16 TXQ Memory Information Register (0x08): TXMIR
This register indicates the amount of free memory available in the TXQ of the QMU module.
Micrel Confidential
Bit
15-11
10
9
8
7
6
5
4
3
2
1
0
Bit
15-13
12-0
November 2005
Default Value
-
0x0
0x0
-
0x0
0x0
0x0
0x0
0x0
0x0
-
0x0
Default Value
-
-
R/W
RO
RW
RW
RO
RW
RW
RW
RW
RW
RW
RO
RW
R/W
RO
RO
Description
Reserved
RXFCE Receive Flow Control Enable
When this bit is set, the KSZ8842M will acknowledge a PAUSE frame from the receive
interface; i.e., the outgoing packets are pending in the transmit buffer until the PAUSE
frame control timer expires. When this bit is cleared, flow control is not enabled.
RXEFE Receive Error Frame Enable
When this bit is set, CRC error frames are allowed to be received into the RX queue.
When reset, all CRC error frames are discarded.
Reserved
RXBE Receive Broadcast Enable
When this bit is set, the RX module receives all the broadcast frames.
RXME Receive Multicast Enable
When this bit is set, the RX module receives all the multicast frames (including
broadcast frames).
RXUE Receive Unicast
When this bit is set, the RX module receives unicast frames that match the 48-bit
Station MAC address of the module.
RXRA Receive All
When this bit is set, the KSZ8842M receives all incoming frames, regardless of the
frame’s destination address.
RXSCE Receive Strip CRC
When this bit is set, the KSZ8842M strips the CRC on the received frames. Once
cleared, the CRC is stored in memory following the packet.
QMU Receive Multicast Hash-Table Enable
When this bit is set, this bit enables the RX function to receive multicast frames that
pass the CRC Hash filtering mechanism.
Reserved
RXE Receive Enable
When this bit is set, the RX block is enabled and placed in a running state. When
reset, the receive process is placed in the stopped state upon completing reception of
the current frame.
Description
Reserved
TXMA Transmit Memory Available
The amount of memory available is represented in units of byte. The TXQ memory is
used for both frame payload, control word. There is total 4096 bytes in TXQ.
Note: Software must be written to ensure that there is enough memory for the next
transmit frame including control information before transmit data is written to the TXQ.
59
KSZ8842-16/32 MQL/MVL
Rev. 1.4