KSZ8842-16MQL Micrel Inc, KSZ8842-16MQL Datasheet - Page 63

IC SWITCH 10/100 16BIT 128PQFP

KSZ8842-16MQL

Manufacturer Part Number
KSZ8842-16MQL
Description
IC SWITCH 10/100 16BIT 128PQFP
Manufacturer
Micrel Inc
Datasheets

Specifications of KSZ8842-16MQL

Data Rate
100Mbps
Controller Type
Ethernet Switch Controller
Interface
PCI
Voltage - Supply
3.1 V ~ 3.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-MQFP, 128-PQFP
No. Of Ports
1
Ethernet Type
IEEE 802.3u
Supply Current
122mA
Supply Voltage Range
3.1V To 3.5V
Operating Temperature Range
0°C To +70°C
Digital Ic Case Style
QFP
No. Of
RoHS Compliant
Number Of Primary Switch Ports
2
Internal Memory Buffer Size
32
Operating Supply Voltage (typ)
3.3V
Fiber Support
Yes
Integrated Led Drivers
Yes
Phy/transceiver Interface
MII
Power Supply Type
Analog/Digital
Package Type
PQFP
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
3.5V
Operating Supply Voltage (min)
3.1V
Operating Temperature Classification
Commercial
Interface Type
PCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
576-1634 - BOARD EVALUATION KSZ8842-16MQL
Current - Supply
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
576-1478-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
KSZ8842-16MQL
Manufacturer:
Micrel Inc
Quantity:
10 000
Part Number:
KSZ8842-16MQLI
Manufacturer:
MICREL
Quantity:
760
Bank 18 Interrupt Status Register (0x02): ISR
This register contains the status bits for all QMU and other interrupt sources.
When the corresponding enable bit is set, it causes the interrupt pin to be asserted.
This register is usually read by the host CPU and device drivers during interrupt service routine or polling. The register bits
are not cleared when read. The user has to write “1” to clear
Micrel Confidential
Bit
15
14
13
12
11
10
9
8
7
6-0
November 2005
Default Value
0x0
0x0
0x0
0x0
0x0
0x0
0x1
0x1
0x0
-
R/W
RO
(W1C)
RO
(W1C)
RO
(W1C)
RO
RO
(W1C)
RO
RO
(W1C)
RO
(W1C)
RO
(W1C)
RO
LCIS Link Change Interrupt Status
When this bit is set, it indicates that the link status has changed from link up to link
down, or link down to link up.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
TXIS Transmit Status
When this bit is set, it indicates that the TXQ MAC has transmitted at least a frame on
the MAC interface and the QMU TXQ is ready for new frames from the host.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
RXIS Receive Interrupt Status
When this bit is set, it indicates that the QMU RXQ has received a frame from the
MAC interface and the frame is ready for the host CPU to process.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
RXOIS Receive Overrun Interrupt Status
When this bit is set, it indicates that the Receive Overrun status has occurred.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
TXPSIE Transmit Process Stopped Status
When this bit is set, it indicates that the Transmit Process has stopped.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
RXPSIE Receive Process Stopped Status
When this bit is set, it indicates that the Receive Process has stopped.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
RXEFIE Receive Error Frame Interrupt Status
When this bit is set, it indicates that the Receive error frame status has occurred.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
Reserved
Description
Reserved
Reserved
63
KSZ8842-16/32 MQL/MVL
Rev. 1.4

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