IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 134

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
5
address bus of the interface can work in the multiplexed on non-multiplexed mode. In the non-multiplexed mode, the ALE pin should be connected to
high. In the multiplexed mode, data bus and address bus should be externally connected.
5.1
be accessed by the microprocessor.
Table 61: T1/J1 Mode Selection Register
5.1.1
Programming Information
Table 62: E1 Mode Register Map - Direct Register
01D ~ 01F 09D ~ 09F 11D ~ 11F 19D ~ 19F 21D ~ 21F 29D ~ 29F 31D ~ 31F 39D ~ 39F
015 ~ 017 095 ~ 097
Framer 1
00A
00D
00E
01A
01B
01C
000
001
002
003
004
005
006
007
008
00F
010
011
012
013
014
018
019
The Micro-Processor Interface provides the logic to connect the microprocessor interface. For all accesses, CS must be low. The data bus and
The registers are divided into two parts: E1 part and T1/J1 part. Before operation, the TEMODE (b0, 400H) must be set to specify which part to
When the TEMODE (b0, 400H) is logic 0, the E1 mode registers are accessed.
PROGRAMMING INFORMATION
REGISTER MAP
E1 MODE REGISTER MAP
Framer 2
08D
09C
080
081
082
083
084
085
086
087
088
08A
08E
08F
090
091
092
093
094
098
099
09A
09B
115 ~ 117
Framer 3
10A
10D
10E
11C
100
101
102
103
104
105
106
107
108
10F
110
112
113
114
118
119
11A
11B
111
Address
400
195 ~ 197 215 ~ 217 295 ~ 297 315 ~ 317 395 ~ 397
Framer4
18D
19C
180
181
182
183
184
185
186
187
188
18A
18E
18F
190
191
192
193
194
198
199
19A
19B
E1 Address
00B
00C
009
Framer 5
20A
20D
20E
21A
21B
21C
200
201
202
203
204
205
206
207
208
20F
210
211
212
213
214
218
219
Framer 6
28D
29C
280
281
282
283
284
285
286
287
288
28A
28E
28F
290
291
292
293
294
298
299
29A
29B
Framer 7
124
30A
30D
30E
31A
31B
31C
300
301
302
303
304
305
306
307
308
30F
310
311
312
313
314
318
319
Framer8
38A
38D
38E
38F
390
393
39A
39B
39C
380
381
382
383
384
385
386
387
388
391
392
394
398
399
T1/E1 Mode Selection
Receive Path Frame Pulse Configuration
Register
Transmit Side System Interface Options
Receive Side System Interface Options
TRSI Parity Configuration and Status
HDLC Micro Select/Framer Reset
RESI Frame Pulse Configuration
TRSI Frame Pulse Configuration
Chip ID/ Global PMON Update
Transmit Path Configuration
Receive Path Line Options
PRGD Positioning/Control
RESI Parity Configuration
Transmit Timing Options
RESI Time Slot Offset
TRSI Time Slot Offset
Interrupt Source #1
Interrupt Source #2
Framer Interrupt ID
RESI Configuration
TRSI Configuration
RESI Bit Offset
TRSI Bit Offset
Clock Monitor
T1 / E1 / J1 OCTAL FRAMER
Diagnostic
Reserved
Reserved
Reserved
Reserved
Register
March 5, 2009