IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 60

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
3.11.2.2
signal on the RSCKn pin and framing signal on the RSFSn pin to output
the data on each RSDn pin.
1.544Mb/s.
of SF/ESF, every second F-bit, the first F-bit of every 12 frames (in SF
format) or every 24 frames (in ESF format). All the indications are
selected by the RSFSP (b2, T1/J1-001H) and ALTIFP (b1, T1/J1-001H).
The valid polarity of RSFSn is configured by the FPINV (b6, T1/J1-
078H).
face is clocked by RSCKn. The active edge of RSCKn to update the
Functional Description
In the Receive Clock Master mode, each framer uses its own clock
In the Receive Clock Master Mode, the bit rate on the RSDn pin is
In the Receive Clock Master Mode, RSFSn can indicate each F-bit
In the Receive Clock Master Mode, the data on the system inter-
RSCKn
RSFSn
RSCK is 1.544M
RSFSn
RSDn
RSDn
When the RSCKRISE (b3, T1/J1-003H) is logic 0:
When the RSCKRISE (b3, T1/J1-003H) is logic 1:
Receive Clock Master Mode
Figure 31. T1/J1 Receive Clock Master Full T1/J1 Mode - Functional Timing Example
1
1
2
2
3
3
4
CH24
4
CH24
5
5
6
6
7
7
8
8
F
F
1
1
50
2
data on RSDn and RSFSn is determined by the RSCKRISE(b3, T1/J1-
003H).
Clock Master Full T1/J1 Mode and Receive Clock Master Fractional T1/
J1 Mode.
3.11.2.2.1
Master mode, the special feature in this mode (refer to Figure 15) is that
RSCKn is a standard 1.544MHz clock, and the data in all 24 channels in
a standard T1/J1 frame is clocked out by RSCKn.
channel is the first bit to be output.
2
3
The Receive Clock Master Mode includes two sub-modes: Receive
Besides all the common functions described in the Receive Clock
Figure 31 shows the functional timing examples. Bit 1 of each
3
CH1
4
CH1
4
5
5
Receive Clock Master Full T1/J1 Mode
6
6
7
7
8
8
1
1
2
T1 / E1 / J1 OCTAL FRAMER
2
CH2
3
CH2
3
4
4
5
5
March 5, 2009