IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 283

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
IEEE STD 1149.1 JTAG Test Access Port
Table 69: TAP Controller State Description
Test Logic Reset In this state, the test logic is disabled to continue normal operation of the device. During initialization, the device initializes the instruction register
Select-DR-Scan This is a temporary controller state and the instruction does not change in this state. The test data register selected by the current instruction
Select-IR-Scan This is a temporary controller state. The test data register selected by the current instruction retains its previous state. If TMS is held low and a ris-
Run-Test/Idle
Capture-DR
Update-DR
Capture-IR
Pause-DR
Pause-IR
Exit1-DR
Exit2-DR
Shift-DR
Exit1-IR
Shift-IR
STATE
This is a controller state between scan operations. Once in this state, the controller remains in the state as long as TMS is held low. The instruc-
In this controller state, the test data register connected between TDI and TDO as a result of the current instruction shifts data on stage toward its
The pause state allows the test controller to temporarily halt the shifting of data through the test data register in the serial path between TDI and
The Boundary Scan Register is provided with a latched parallel output to prevent changes while data is shifted in response to the EXTEST and
In this controller state, the shift register contained in the instruction register loads a fixed value of '100' on the rising edge of TCK. This supports
In this state, the shift register contained in the instruction register is connected between TDI and TDO and shifts data one stage towards its serial
with the IDCODE instruction.
Regardless of the original state of the controller, the controller enters the Test-Logic-Reset state when the TMS input is held high for at least 5 ris-
ing edges of TCK. The controller remains in this state while TMS is high.
tion register and all test data registers retain their previous state. When TMS is high and a rising edge is applied to TCK, the controller moves to
the Select-DR state.
retains its previous state. If TMS is held low and a rising edge is applied to TCK when in this state, the controller moves into the Capture-DR state
and a scan sequence for the selected test data register is initiated. If TMS is held high and a rising edge applied to TCK, the controller moves to
the Select-IR-Scan state.
In this state, the Boundary Scan Register captures input pin data if the current instruction is EXTEST or SAMPLE/PRELOAD. The instruction does
not change in this state. The other test data registers, which do not have parallel input, are not changed. When the TAP controller is in this state
and a rising edge is applied to TCK, the controller enters the Exit1-DR state if TMS is high or the Shift-DR state if TMS is low.
serial output on each rising edge of TCK. The instruction does not change in this state. When the TAP controller is in this state and a rising edge
is applied to TCK, the controller enters the Exit1-DR state if TMS is high or remains in the Shift-DR state if TMS is low.
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-DR state,
which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Pause-DR state. The test
data register selected by the current instruction retains its previous value and the instruction does not change during this state.
TDO. For example, this state could be used to allow the tester to reload its pin memory from disk during application of a long test sequence. The
test data register selected by the current instruction retains its previous value and the instruction does not change during this state. The controller
remains in this state as long as TMS is low. When TMS goes high and a rising edge is applied to TCK, the controller moves to the Exit2-DR state.
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-DR state,
which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Shift-DR state. The test
data register selected by the current instruction retains its previous value and the instruction does not change during this state.
SAMPLE/PRELOAD instructions. When the TAP controller is in this state and the Boundary Scan Register is selected, data is latched into the par-
allel output of this register from the shift-register path on the falling edge of TCK. The data held at the latched parallel output changes only in this
state. All shift-register stages in the test data register selected by the current instruction retain their previous value and the instruction does not
change during this state.
ing edge is applied to TCK when in this state, the controller moves into the Capture-IR state, and a scan sequence for the instruction register is ini-
tiated. If TMS is held high and a rising edge is applied to TCK, the controller moves to the Test-Logic-Reset state. The instruction does not change
during this state.
fault-isolation of the board-level serial test data path. Data registers selected by the current instruction retain their value and the instruction does
not change during this state. When the controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-IR state if TMS
is held high, or the Shift-IR state if TMS is held low.
output on each rising edge of TCK. The test data register selected by the current instruction retains its previous value and the instruction does not
change during this state. When the controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-IR state if TMS is
held high, or remains in the Shift-IR state if TMS is held low.
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-IR state,
which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Pause-IR state. The test
data register selected by the current instruction retains its previous value and the instruction does not change during this state.
The pause state allows the test controller to temporarily halt the shifting of data through the instruction register. The test data register selected by
the current instruction retains its previous value and the instruction does not change during this state. The controller remains in this state as long
as TMS is low. When TMS goes high and a rising edge is applied to TCK, the controller moves to the Exit2-IR state.
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DESCRIPTION
T1 / E1 / J1 OCTAL FRAMER
March 5, 2009