IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 229

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
T1 / J1 Interrupt ID (00EH)
the interrupt, the corresponding bit in the INT[8:1] will be high.
T1 / J1 Pattern Generator / Detector Positioning / Control (00FH)
This register selects which framer will use the PRGD and how the PRGD will be used.
PRGDSEL[2:0]:
Nx56k_GEN:
Nx56k_DET:
RXPATGEN:
Programming Information
Bit Name
Bit Name
Default
Default
Bit No.
Bit No.
Type
Type
This register indicates which one of the eight framers introduced the interrupt INT pin to logic low. When any one of the eight framers introduced
The IDT82V2108 has only one Pattern Generator/Detector (PRGD) shared by all eight framers. At one time, only one framer can use this PRGD.
The PRGDSEL[2:0] select one of the eight framers to be tested by the PRGD block.
This bit is invalid when the UNF_GEN (b1, T1/J1-00FH) is logic 1.
= 0: Eight bits are all replaced with the PRGD pattern when one channel is selected by the TPLC or RPLC.
= 1: The 7 most significant bits are replaced with the PRGD pattern when one channel is selected by the TPLC or RPLC.
This bit is invalid when the UNF_DEL (b0, T1/J1-00FH) is logic 1.
= 0: Eight bits are all detected by the PRGD when one channel is selected by the TPLC or RPLC.
= 1: The 7 most significant bits are detected by the PRGD when one channel is selected by the TPLC or RPLC.
= 0: The pattern in PRGD is generated in the transmit path and is detected in the receive path.
= 1: The pattern in PRGD is generated in the receive path and is detected in the transmit path.
PRGDSEL[2]
INT[8]
R/W
R
7
0
7
0
PRGDSEL[1]
INT[7]
R/W
R
6
0
6
0
PRGDSEL[0]
INT[6]
R/W
PRGDSEL[2:0]
R
5
0
5
0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Nx56k_GEN
INT[5]
R/W
R
4
0
4
0
219
Tested Framer
Framer 1
Framer 2
Framer 3
Framer 4
Framer 5
Framer 6
Framer 7
Framer 8
Nx56k_DET
INT[4]
R/W
R
3
0
3
0
RXPATGEN
INT[3]
R/W
R
2
0
2
0
T1 / E1 / J1 OCTAL FRAMER
UNF_GEN
INT[2]
R/W
R
1
0
1
0
March 5, 2009
UNF_DET
INT[1]
R/W
R
0
0
0
0