IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 71

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
3.13.1.2
mit Side System Common Clock A (TSCCKA) and Transmit Side Sys-
tem Common Clock B (TSCCKB) provided by the system side are used
TSSIGn is used as TSFSn to output a framing pulse to indicate the first
bit of each Basic Frame.
2.048Mb/s.
cessed clock signal on the LTCKn pin to sample/update the data on the
system interface. The active edge of LTCKn to sample the data on the
TSDn pin is determined by the DE (b4, E1-018H). The active edge of
Functional Description
In the Transmit Clock Master mode (refer to Figure 43), the Trans-
In the Transmit Clock Master mode, the multi-functional pin TSFSn/
In the Transmit Clock Master mode, the bit rate on the TSDn pin is
In the Transmit Clock Master mode, each framer uses its own pro-
TSCFS
TSCCKB
TSSIGn
TSDn
Transmit Clock Master Mode
Figure 42. E1 Transmit Clock Slave External Signaling Mode - Functional Timing Example 2
TSCCKA
TSCCKB
TSD[1:8] *
TSFS[1:8] *
Note: * TSD, TSFS are timed to LTCK
1
X
X
2
X
3
The CMS (b2, E1-018H) is logic 1, i.e., the bankplane clock rate is 4.096Mbit/s.
X
4
The FE(b3, E1-018H) is logic 1 and the DE (b4, E1-018H) is logic 1.
Transmit
Interface
System
TS31
A
5
Figure 43. Transmit Clock Master Mode
B
6
The COFF (b4, E1-01CH) is in its default value.
C
7
D
8
1
P
Generator
Frame
2
X
61
3
X
as one of the reference clocks for the transmit jitter attenuator DPLL for
all eight framers (refer to Chapter 3.20 Transmit Clock for details).
LTCKn to update the pulse on the TSFSn pin is determined by the TSF-
SRISE (b2, E1-002H).
slot is the first bit to be transmitted.
X
4
Figure - 42 shows the functional timing examples. Bit 1 of each time
TS0
X
5
(The 'X' represent the filled bits and has no meaning.)
TRANSMITTER
X
6
X
7
DPLL
X
8
X
1
X
2
T1 / E1 / J1 OCTAL FRAMER
3
X
LRCK[1:8]
LTCK[1:8]
TS1
LTD[1:8]
4
X
A
5
6
B
March 5, 2009