IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 191

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
E1 RHDLC #1, #2, #3 Status (04AH, 0CAH, 14AH, 1CAH, 24AH, 2CAH, 34AH, 3CAH)
E1-00AH).
FE:
OVR:
COLS:
PKIN:
PBS[2:0]:
INTR:
7E opening flag sequence which activates the HDLC link; 2. A packet was received; 3. Change of link status; 4. Exceeding the set point of the FIFO
which is defined in the INTC[6:0] (b6~0, E1-049H); 5. Over-writing the FIFO.
Programming Information
Bit Name
Default
Bit No.
Type
Selection of the RHDLC block (#1, #2, or #3) whose registers are visible on the microprocessor interface is done via the RHDLCSEL[1:0] (b7~6,
= 0: The FIFO is loaded with data.
= 1: The FIFO is empty.
The overwritten condition occurs when data is written over unread data in the FIFO buffer. This bit is cleared to ‘0’ after the register is read.
= 0: No overwriting occurs.
= 1: The FIFO is overwritten, and then the FIFO is reset, which cause the COLS and PKIN to be reset to logic 0.
This bit reflects the HDLC link status change.
= 0: Normal operation.
= 1: The first HDLC opening flag sequence (7E) activating the HDLC or the HDLC abort sequence (7F) deactivating the HDLC is detected.
This bit is cleared to ‘0’ after the bit is read, or after the OVR transits to be logic 1, or after the EN is clear.
= 0: A HDLC packet has not been written into the FIFO.
= 1: A HDLC packet has been written into the FIFO.
This bit is cleared to ‘0’ after the bit is read, or after the OVR transits to logic 1.
The PBS[2:0] indicate the status of the last byte read from the FIFO.
= 0: No interrupt sources in the HDLC Receiver block occur
= 1: Any one of the interrupt sources in the HDLC Receiver block occurs. The interrupt sources in the HDLC Receiver are: 1. Receiving the first
This bit is cleared to ‘0’ after the bit is read.
PBS[2:0]
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Normal data
A dummy byte to indicate the first HDLC opening flag sequence (7E) was detected, which means the HDLC link became active.
A dummy byte to indicate the HDLC abort sequence (7F) was detected, which means the HDLC link became inactive.
Reserved.
The last byte of a non-aborted HDLC packet was received. The HDLC packet is in an integer number of bytes and has no FCS error.
The last byte of a non-aborted HDLC packet was received and a non-integer number of bytes are in the packet.
The last byte of a non-aborted HDLC packet was received. The HDLC packet is in an integer number of bytes and has FCS errors.
The last byte of a non-aborted HDLC packet was received. The HDLC packet is in a non-integer number of bytes and has FCS errors.
FE
R
X
7
OVR
R
6
X
COLS
R
X
5
PKIN
R
X
4
181
Status of the Data
PBS[2]
R
X
3
PBS[1]
R
2
X
T1 / E1 / J1 OCTAL FRAMER
PBS[0]
R
X
1
March 5, 2009
INTR
R
X
0