IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 271
IDT82V2108PX
Manufacturer Part Number
IDT82V2108PX
Description
IC FRAMER T1/J1/E1 8CH 128-PQFP
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT82V2108PX8.pdf
(292 pages)
Specifications of IDT82V2108PX
Controller Type
T1/E1/J1 Framer
Interface
Parallel
Voltage - Supply
2.97 V ~ 3.63 V
Current - Supply
160mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
128-MQFP, 128-PQFP
Screening Level
Industrial
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
82V2108PX
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IDT82V2108
T1 / J1 PRGD Shift Register Length (062H)
T1 / J1 PRGD Tap (063H)
equal to the value of ‘PT[4:0] + 1’. In application, the PT is always less than the PL.
T1 / J1 PRGD Error Insertion (064H)
EVENT:
set from ‘0’ to ‘1’ again.
EIR[2:0]:
value to another non-zero value, it is recommended to set the EIR[2:0] to ‘000’ first, then set the EIR[2:0] to the desired value.
Programming Information
Bit Name
Bit Name
Bit Name
Default
Default
Bit No.
Bit No.
Default
Bit No.
Type
Type
These bits determine the length of the valid data in the PRGD pattern insertion register. The length is equal to the value of ‘PL[4:0] + 1’.
These bits determine the feedback tap position of the generated pseudo random pattern before it is transmitted. The feedback tap position is
A single bit error is generated when the state of this bit is changed from ‘0’ to ‘1’. To insert another bit error, this bit must be cleared to ‘0’, and then
The EIR[2:0] bits determine the bit error rate that will be inserted in the PRGD test pattern. If the bit error rate is changed from one non- zero
Type
7
7
7
Reserved
Reserved
6
6
6
Reserved
5
5
5
EIR[2:0]
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
0 1 0
PL[4]
PT[4]
R/W
R/W
4
4
0
4
0
261
No error inserted
No error inserted
Bit error rate
10
10
10
10
10
10
EVENT
-2
-3
-4
-5
-6
-7
PT[3]
PL[3]
R/W
R/W
R/W
3
0
3
0
3
0
EIR[2]
PL[2]
PT[2]
R/W
R/W
R/W
2
0
2
0
2
0
T1 / E1 / J1 OCTAL FRAMER
EIR[1]
PL[1]
PT[1]
R/W
R/W
R/W
1
0
1
0
1
0
March 5, 2009
EIR[0]
PL[0]
PT[0]
R/W
R/W
R/W
0
0
0
0
0
0
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