IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 47

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
3.11.1.2.2
Master mode, the special feature in this mode (refer to Figure 17) is that
gapped during those time slots with their DTRKC/NxTS (b6, E1-RPLC-
indirect register - 20~3FH) in Receive Payload Control are logic 1. It
clocks out during those time slots with their DTRKC/NxTS_IDLE (b6, E1-
RPLC-indirect register - 20~3FH) set to logic 0. The data in the corre-
sponding gapped time slot is a don’t-care. Figure 18 shows the func-
tional timing examples. Bit 1 of each time slot is the first bit to be output.
ITU recommendation G.802 where an E1 clock is output as a 193-bit T1
clock. In this mode, the RSCKn that starts from the 2nd bit of TS26 and
ends at the last bit of the same Basic Frame are gapped, and the TS16
is also gapped. Thus, the DTRKC/NxTS (b6, E1-RPLC-indirect register -
20~3FH) of the time slots whose clock is gapped are invalid. The gap-
ping of the remaining time slots is still determined by the DTRKC/NxTS
(b6, E1-RPLC-indirect register - 20~3FH), and the data in the corre-
sponding gapped time slot is a don't-care.
Functional Description
Besides all the common functions described in the Receive Clock
In the Receive Clock Master Fractional E1 mode, RSCKn is
The Receive Clock Master Fractional E1 with F-bit mode supports
Receive Clock Master Fractional E1 (with F-bit) Mode
RSD[1:8] *
RSFS[1:8] *
RSCK[1:8]
Note: * RSD, RSFS are timed to gapped RSCK
Figure 17. Receive Clock Master Fractional E1 or T1/J1 Mode
Interface
Receive
System
Processor
Frame
37
RSCKn is a gapped 2.048MHz clock (no clock signal during the selected
time slot).
RECEIVER
DPLL
FIFO
T1 / E1 / J1 OCTAL FRAMER
LRCK[1:8]
LRD[1:8]
March 5, 2009