IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 197

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
E1 THDLC #1, #2, #3 Transmit Data (055H, 0D5H, 155H, 1D5H, 255H, 2D5H, 355H, 3D5H)
E1-00AH).
E1 ELSB Interrupt Enable / Status (059H, 0D9H, 159H, 1D9H, 259H, 2D9H, 359H, 3D9H)
SLIPE:
SLIPD:
SLIPI:
E1 ELSB Idle Code (05AH, 0DAH, 15AH, 1DAH, 25AH, 2DAH, 35AH, 3DAH)
is the first bit to be inserted.
register is written to when the framer is out of frame.
Programming Information
Bit Name
Bit Name
Bit Name
Default
Default
Default
Bit No.
Bit No.
Bit No.
Type
Type
Type
Selection of the THDLC block (#1, #2, or #3) whose registers are visible on the microprocessor interface is done via the THDLCSEL[1:0] (b5~4,
The content is the data to be transmitted. It is serially transmitted (TD[0] is the first).
= 0: Disable the interrupt on the INT pin when a slip occurs.
= 1: Enable the interrupt on the INT pin when a slip occurs.
This bit makes sense only when the SLIPI is logic 1.
= 0: The latest slip is due to the Elastic Store Buffer being empty; a frame was duplicated.
= 1: The latest slip is due to the Elastic Store Buffer being full; a frame was deleted.
= 0: No slip occurs.
= 1: A slip occurs.
This bit is cleared to ‘0’ after the bit is read.
These bits set the idle code that will replace the data on RSDn/MRSD when it is out of Basic Frame and the TRKEN (b1, E1-001H) is logic 1. D7
The writing of the idle code pattern is asynchronous with respect to the output data clock. One time slot of idle code data will be corrupted if the
TD[7]
R/W
R/W
D7
X
7
7
7
1
TD[6]
R/W
R/W
D6
6
X
6
6
1
Reserved
TD[5]
R/W
R/W
D5
X
5
5
5
1
TD[4]
R/W
R/W
D4
X
4
4
4
1
187
TD[3]
R/W
R/W
D3
X
3
3
3
1
SLIPE
TD[2]
R/W
R/W
R/W
D2
2
X
2
0
2
1
T1 / E1 / J1 OCTAL FRAMER
SLIPD
TD[1]
R/W
R/W
D1
X
R
X
1
1
1
1
March 5, 2009
TD[0]
SLIPI
R/W
R/W
D0
X
R
X
0
0
0
1