IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 41

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
the data streams for all eight framers. RSCFS asserts on each Basic
Frame and its valid polarity is configured by the FPINV (b6, E1-011H).
The framing signals on RSCFS can also be ignored by setting the
FPMODE (b5, E1-011H) to ‘0’.
2.048Mb/s.
Pulse (RSFSn) can be configured by the PERTS_RSFS (b3, E1-00EH)
and REF_MRSFS (b2, E1-00EH) to output all zeros, to indicate the
frame position or to output the same pulse as RSCFS. When it is defined
to indicate the frame position, it can indicate the first bit of a Basic
Frame, Signaling Multi-Frame, CRC-Multiframe, or both the Signaling
and CRC-multiframe. This selection is made by the ROHM, BRXSMFP,
BRXCMFP, ALTIFP (b3, b2, b1, b0, E1-011H). When RSFSn is for fram-
Table 12: Active Edge Selection of RSCCK (in E1 Receive Clock
Slave RSCK Reference Mode)
each time slot is the first bit to be output.
Slave mode, the special feature in this mode is that the multi-functional
Functional Description
Note:
If the setting of the FE (b3, E1-010H) and DE (b4, E1-010H) is different, RSFSn will be
one clock edge ahead of RSDn.
The FE (b3, E1-010H) of the eight framers should be set to the same value to ensure
RSCFS for the eight framers is sampled on the same active edge.
There is a special case when the CMS (b2, E1-010H) is logic 1 and the DE (b4, E1-
010H) is equal to FE (b3, E1-010H). The RSD_RSCFS_EDGE (b5, E1-014H) is invalid
and the signal on the RSDn and the RSFSn pins are updated on the first active edge of
RSCCK.
In the Receive Clock Slave Mode, the bit rate on the RSDn pin is
In the Receive Clock Slave Mode, the Receive Side System Frame
Figure 10 & Figure 11 show the functional timing examples. Bit 1 of
Besides all the common functions described in the Receive Clock
RSCFS
RSFSn
RSDn
RSCCK
RSCFS *
RSD[1:8] *
RSFS[1:8] *
RSCK[1:8]
Note: * RSCFS, RSD, RSFS are timed to RSCCK
Bit Determining the Active Edge of RSCCK
DE (b4, E1-010H)
FE (b3, E1-010H)
Interface
Receive
Figure 9. Receive Clock Slave RSCK Reference Mode
System
Elastic
Store
8kHz
Processor
31
Divider
Frame
ing pulse indication, the valid polarity of it is configured by the FPINV
(b6, E1-011H). In this case, if the FPMODE (b5, E1-011H) is low, RSFSn
can only indicate the Basic Frame no matter what the setting in the
ROHM, BRXSMFP, BRXCMFP, ALTIFP (b3, b2, b1, b0, E1-011H) is.
Clock Slave RSCK Reference Mode and Receive Clock Slave External
Signaling Mode.
3.11.1.1.1
clocked by RSCCK. The active edge of RSCCK to sample the pulse on
RSCFS or to update the data on the RSDn and RSFSn pins is deter-
mined by the following bits in the registers (refer to Table 12).
pin RSCKn/RSSIGn is used as RSCKn to output a reference clock.
RSCKn can be chosen by the RSCKSEL (b5, E1-001H) to output a jitter
attenuated 2.048MHz (i.e., smoothed LRCKn) or 8KHz clock (smoothed
LRCKn divided by 256).
The Receive Clock Slave Mode includes two sub-modes: Receive
In this mode (refer to Figure 9), the data on the system interface is
Receive Clock Slave RSCK Reference Mode
RECEIVER
DPLL
FIFO
T1 / E1 / J1 OCTAL FRAMER
LRCK[1:8]
LRD[1:8]
March 5, 2009