IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 154

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
E1 Receive Backplane Frame Pulse Configuration (011H, 091H, 111H, 191H, 211H, 291H, 311H, 391H)
FPINV:
FPMODE:
must be ‘0’.
ROHM:
TS0 and TS16. Details are tabulated in the following table.
BRXSMFP, BRXCMFP:
the output signal seen on the RSFSn pin. Details are tabulated in the following table.
ALTIFP:
sion of every other framing pulse. The following table shows the details for the different configurations of RSFSn.
indicate the first bit of a Basic Frame of the selected first framer no matter what is set in the ROHM, BRXSMFP, BRXCMFP and ALTIFP.
Programming Information
Bit Name
ROHM
Default
Bit No.
Type
= 0: Framing pulse RSCFS and RSFSn/MRSFS are active high.
= 1: Framing pulse RSCFS and RSFSn/MRSFS are active low.
When this bit is used to indicate the active pulse for RSCFS or MRSFS, then it should be set to the same value for all eight framers.
This bit decides whether to use RSCFS as the framing pulse or not. In Receive Clock Master mode (RSCKSLV = 0, b5, E1-010H), the FPMODE
= 0: RSCFS/MRSCFS is unused.
= 1: RSCFS/MRSCFS is used.
In Receive Multiplexed mode, the FPMODE in all eight framers should be set to the same value.
When the PERTS_RSFS and the REF_MRSFS (b3~2, E1-00EH) are ‘1’ and ‘0’ respectively, this bit decides whether to use RSFSn to indicate
When the PERTS_RSFS and the REF_MRSFS (b3~2, E1-00EH) are ‘1’ and ‘0’ respectively, these two bits, together with the ALTIFP bit, select
When the RSFSn pin is configured to output the framing pulse for Basic Frame, Signaling Multiframe or CRC Multiframe, this bit permits suppres-
In Receive Multiplexed mode, when the PERTS_RSFS and the REF_MRSFS (b3~2, E1-00EH) are ‘1’ and ‘0’ respectively, the MRSFS can only
0
0
0
0
0
0
0
0
1
BRXSMFP
Reserved
X
0
0
0
0
1
1
1
1
7
BRXCMFP
X
0
0
1
1
0
0
1
1
FPINV
R/W
6
0
ALTIFP
X
0
1
0
1
0
1
0
1
FPMODE
R/W
RSFSn asserts for 1 bit cycle on the first bit of each Basic Frame output on RSDn.
RSFSn asserts for 1 bit cycle on the first bit of every second Basic Frame output on RSDn.
RSFSn asserts for 1 bit cycle on the first bit of the first frame of each CRC Multi-Frame output on RSDn (in
case CRC Multi-Frame is disabled, RSFSn asserts every 16 frames).
RSFSn asserts for 1 bit cycle on the first bit of the first frame of every second CRC Multi-Frame output on
RSDn (in case CRC Multi-Frame is disabled, RSFSn asserts every 32 frames).
RSFSn asserts for 1 bit cycle on the first bit of the first frame of each Signaling Multi-Frame output on
RSDn (in case Signaling Multi-Frame is disabled, RSFSn asserts every 16 frames).
RSFSn asserts for 1 bit cycle on the first bit of the first frame of every second Signaling Multi-Frame out-
put on RSDn (in case Signaling Multi-Frame is disabled, RSFSn asserts every 32 frames).
RSFSn goes high/low at the start of the first bit of the first frame of each Signaling Multi-Frame, and goes
the opposite at the end of the first bit of the first frame of each CRC Multi-Frame.
RSFSn goes high/low at the start of the first bit of the first frame of every second Signaling Multi-Frame,
and goes the opposite at the end of the first bit of the first frame of every second CRC Multi-Frame.
The RSFSn pin pulses during the entire TS0 period and the entire TS16 period.
5
1
Reserved
4
144
ROHM
R/W
RSFSn / MRSFS Indication
3
0
BRXSMFP
R/W
2
0
T1 / E1 / J1 OCTAL FRAMER
BRXCMFP
R/W
1
0
March 5, 2009
ALTIFP
R/W
0
0