IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 145

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
E1 Transmit Side System Interface Options (003H, 083H, 103H, 183H, 203H, 283H, 303H, 383H)
TSSIG_EN:
MTBS:
E1 Transmit Timing Options (004H, 084H, 104H, 184H, 204H, 284H, 304H, 384H)
TJATREF_SEL[2:0] - Transmit Jitter Attenuation DPLL Input Reference Clock Selection
LTCK_SEL[2:0] - Line Transmit Clock (LTCKn) Selection
Programming Information
Bit Name
Bit Name
Default
Default
Bit No.
Bit No.
Type
Type
In Transmit Clock Slave mode (TSCKSLV = 1, b5, E1-018H), this bit configures the transmit side system interface.
= 0: Transmit Clock Slave TSFS Enable mode is selected. The TSFSn/TSSIGn pin is used as TSFSn output.
= 1: Transmit Clock Slave External Signaling mode is selected. The TSFSn/TSSIGn pin is used as TSSIGn input.
In Transmit Multiplexed mode, this bit must be set to ‘1’.
In Transmit Multiplexed mode, this bit determines which multiplexed bus will interface with the corresponding framer.
= 0: The incoming data is taken from the first multiplexed bus (MTSD1, MTSSIG1).
= 1: The incoming data is taken from the second multiplexed bus (MTSD2, MTSSIG2).
The TJATREF_SEL[2:0] select the input reference clock for the TJAT DPLL.
The LTCK_SEL[2:0] select the line transmit clock.
Reserved
7
7
Reserved
TSSIG_EN
R/W
6
6
1
LTCK_SEL[2:0]
TJATREF_SEL[2] TJATREF_SEL[1] TJATREF_SEL[0]
Others
000
001
010
100
011
TJATREF_SEL[2:0]
Reserved
R/W
5
1
5
Others
000
001
010
100
011
MTBS
R/W
R/W
4
0
4
0
135
A smoothed clock output from the TJAT DPLL
Input Reference Clock
TSCCKA / 8
TSCCKB
TSCCKB
TSCCKA
XCK / 24
Line Transmit Clock
LRCK
R/W
TSCCKA / 8
3
0
3
TSCCKB
TSCCKA
XCK / 24
LRCK
LTCK_SEL[2]
R/W
2
2
1
Reserved
T1 / E1 / J1 OCTAL FRAMER
LTCK_SEL[1]
R/W
1
0
1
March 5, 2009
LTCK_SEL[0]
R/W
0
1
0