IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 43

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
3.11.1.1.2
clocked by RSCCK. The active edge of RSCCK used to sample the
Table 13: Active Edge Selection of RSCCK (in E1 Receive Clock
Slave External Signaling Mode)
each time slot is the first bit to be output.
Slave mode, the special feature in this mode is that the multi-functional
pin RSCKn/RSSIGn is used as RSSIGn to output the extracted signaling
bits. The extracted signaling bits are time slot aligned with the data on
the RSDn pin (refer to Figure 7).
bits ABCD on the RSSIGn pin can be forced to be all ones if the OOSM-
FAIS (b2, E1-001H) is set to ‘1’.
Functional Description
Note:
If the setting of the FE (b3, E1-010H) and DE (b4, E1-010H) is different, RSFSn will be
one clock edge ahead of RSDn.
The FE (b3, E1-010H) of the eight framers should be set to the same value to ensure
RSCFS for the eight framers is sampled on the same active edge.
There is a special case when the CMS (b2, E1-010H) is logic 1 and the DE (b4, E1-
010H) is equal to FE (b3, E1-010H). The RSD_RSCFS_EDGE (b5, E1-014H) is invalid
and the signal on the RSDn, RSSIGn and RSFSn pins are updated on the first active
edge of RSCCK.
In this mode (refer to Figure 12), the data on the system interface is
Figure 13 & Figure 14 show the functional timing examples. Bit 1 of
Besides all the common functions described in the Receive Clock
In the Out of Signaling Multi-Frame condition, the output signaling
RSSIGn
RSCFS
RSFSn
RSDn
Receive Clock Slave External Signaling Mode
RSCCK
RSCFS *
RSD[1:8] *
RSFS[1:8] *
RSSIG[1:8] *
Note: * RSCFS, RSD, RSSIG, RSFS are timed to RSCCK
Bit Determining the Active Edge of RSCCK
Figure 12. Receive Clock Slave External Signaling Mode
DE (b4, E1-010H)
FE (b3, E1-010H)
Interface
Receive
System
Elastic
Store
33
Processor
Frame
pulse on RSCFS or to update the data on RSDn, RSFSn and RSSIGn is
determined by the following bits in the registers (refer to Table 13).
RECEIVER
DPLL
FIFO
T1 / E1 / J1 OCTAL FRAMER
LRCK[1:8]
LRD[1:8]
March 5, 2009